Merge pull request #173 from riscv-boom/refactor

[rvc] Fix RVC compatibility with banked I$
riscv-boom · Jan 31, 2019 · 4cf23ef · 4cf23ef
2 parents 3075248 + cb4bc00
commit 4cf23ef
Showing 1 changed file with 19 additions and 8 deletions.
diff --git a/src/main/scala/ifu/fetch.scala b/src/main/scala/ifu/fetch.scala
@@ -244,9 +244,10 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
    val prev_half    = Reg(UInt(coreInstBits.W))
    // Tracks if last fetchpacket contained a half-inst
    val prev_is_half = RegInit(false.B)
-   // Tracks previously fetched pc
-   val prev_fetchedpc = Reg(UInt(vaddrBitsExtended.W))
-   val use_prev = prev_is_half && f3_fetch_bundle.pc === prev_fetchedpc + fetchBytes.U
+   // Tracks nextpc after the previous fetch bundle
+   val prev_nextpc = Reg(UInt(vaddrBitsExtended.W))
+
+   val use_prev = prev_is_half && f3_fetch_bundle.pc === prev_nextpc
    assert(fetch_width >= 4 || !usingCompressed) // Logic gets kind of annoying with fetch_width = 2
    for (i <- 0 until fetch_width)
    {
@@ -270,6 +271,11 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
          // Need special case since 0th instruction may carry over the wrap around
          inst     := f3_imemresp.data(i*coreInstBits+2*coreInstBits-1,i*coreInstBits)
          is_valid := use_prev || !(f3_valid_mask(i-1) && f3_fetch_bundle.insts(i-1)(1,0) === 3.U)
+      } else if (icIsBanked && i == (fetch_width / 2) - 1) {
+         // If we are using a banked I$ we could get cut-off halfway through the fetch bundle
+         inst     := f3_imemresp.data(i*coreInstBits+2*coreInstBits-1,i*coreInstBits)
+         is_valid := !(f3_valid_mask(i-1) && f3_fetch_bundle.insts(i-1)(1,0) === 3.U) &&
+                     !(inst(1,0) === 3.U && !f3_imemresp.mask(i+1))
       } else if (i == fetch_width - 1) {
          inst     := Cat(0.U(16.W), f3_imemresp.data(fetchWidth*coreInstBits-1,i*coreInstBits))
          is_valid := !((f3_valid_mask(i-1) && f3_fetch_bundle.insts(i-1)(1,0) === 3.U) ||
@@ -341,12 +347,17 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
          f3_jal_target,
          nextFetchStart(f3_aligned_pc)))
 
+
    when (f3_valid && f4_ready && !r_f4_req.valid) {
-      prev_is_half := (!(f3_valid_mask(fetchWidth-2) && f3_fetch_bundle.insts(fetchWidth-2)(1,0) === 3.U)
-                    && f3_fetch_bundle.insts(fetchWidth-1)(1,0) === 3.U
-      )
-      prev_half    := f3_fetch_bundle.insts(fetchWidth-1)(15,0)
-      prev_fetchedpc := alignToFetchBoundary(f3_fetch_bundle.pc)
+      val last_idx  = Mux(inLastChunk(f3_fetch_bundle.pc) && icIsBanked.B,
+                          (fetchWidth/2-1).U, (fetchWidth-1).U)
+      prev_is_half := (!(f3_valid_mask(last_idx-1.U) && f3_fetch_bundle.insts(last_idx-1.U)(1,0) === 3.U)
+                    && f3_fetch_bundle.insts(last_idx)(1,0) === 3.U)
+      prev_half    := f3_fetch_bundle.insts(last_idx)(15,0)
+      prev_nextpc  := alignToFetchBoundary(f3_fetch_bundle.pc) + Mux( inLastChunk(f3_fetch_bundle.pc) && icIsBanked.B
+                                                                    , bankBytes.U
+                                                                    , fetchBytes.U)
+
    }
 
    when (f3_valid && f3_btb_resp.valid)