Merge pull request #501 from riscv-boom/chisel34

Bump to Chisel 3.4 | Fix small deprecated items

.circleci/defaults.sh

@@ -111,7 +111,8 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
 REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
 REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
-REMOTE_JAVA_ARGS="-Xmx16G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
+REMOTE_JAVA_OPTS="-Xmx16G -Xss8M"
+REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
 REMOTE_SPEC=$CI_DIR/../abejgonza/cpu2017-1.0.1.iso # TODO: this is temporary until a better location is found
 
 # remote variables (on manager instance)

.circleci/do-rtl-build.sh

@@ -53,7 +53,7 @@ run "export RISCV=\"$TOOLS_DIR\"; \
      export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
      export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
      make -C $REMOTE_SIM_DIR clean; \
-     make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
+     make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$1]}"
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
 # copy back the final build

.gitignore

@@ -5,5 +5,4 @@ target
 lib
 *#
 *~
-project/build.properties
-.nfs*
+.nfs*

CHIPYARD.hash

@@ -1 +1 @@
-239b6b6e095aff7075b25c91c45f35a9bb9a113f
+939e3a9f94d5bfef9671f49c37cd3acd5fc26128

build.sbt

@@ -1,13 +1,4 @@
 organization := "edu.berkeley.cs"
-
-version := "1.0"
-
+version := "3.0"
 name := "boom"
-
-scalaVersion := "2.12.4"
-
-scalacOptions ++= Seq("-Xsource:2.11")
-
-libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.2+"
-
-addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
+scalaVersion := "2.12.10"

project/build.properties

@@ -0,0 +1 @@
+sbt.version=1.3.13

src/main/scala/common/config-mixins.scala

@@ -110,7 +110,7 @@ class WithNSmallBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
               fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
             ),
             dcache = Some(
-              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBEntries=8)
+              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
             ),
             icache = Some(
               ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4)
@@ -157,7 +157,7 @@ class WithNMediumBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
               fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
             ),
             dcache = Some(
-              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBEntries=8)
+              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
             ),
             icache = Some(
               ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4)
@@ -203,7 +203,7 @@ class WithNLargeBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
               fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
             ),
             dcache = Some(
-              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=4, nTLBEntries=16)
+              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16)
             ),
             icache = Some(
               ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)
@@ -251,7 +251,7 @@ class WithNMegaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
               fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
             ),
             dcache = Some(
-              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBEntries=32)
+              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
             ),
             icache = Some(
               ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)
@@ -299,7 +299,7 @@ class WithNGigaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
               fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
             ),
             dcache = Some(
-              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBEntries=32)
+              DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
             ),
             icache = Some(
               ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)

src/main/scala/common/parameters.scala

@@ -90,6 +90,8 @@ case class BoomCoreParams(
   useRVE: Boolean = false,
   useBPWatch: Boolean = false,
   clockGate: Boolean = false,
+  mcontextWidth: Int = 0,
+  scontextWidth: Int = 0,
 
   /* debug stuff */
   enableCommitLogPrintf: Boolean = false,
@@ -106,7 +108,6 @@ case class BoomCoreParams(
   val retireWidth = decodeWidth
   val jumpInFrontend: Boolean = false // unused in boom
 
-
   override def customCSRs(implicit p: Parameters) = new BoomCustomCSRs
 }
 

src/main/scala/exu/core.scala

@@ -355,8 +355,8 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
         "DCache nMSHRs         : " + dcacheParams.nMSHRs,
         "ICache Ways           : " + icacheParams.nWays,
         "ICache Sets           : " + icacheParams.nSets,
-        "D-TLB Entries         : " + dcacheParams.nTLBEntries,
-        "I-TLB Entries         : " + icacheParams.nTLBEntries,
+        "D-TLB Ways            : " + dcacheParams.nTLBWays,
+        "I-TLB Ways            : " + icacheParams.nTLBWays,
         "Paddr Bits            : " + paddrBits,
         "Vaddr Bits            : " + vaddrBits) + "\n"
     + BoomCoreStringPrefix(
@@ -375,6 +375,8 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
   // Breakpoint info
   io.ifu.status  := csr.io.status
   io.ifu.bp      := csr.io.bp
+  io.ifu.mcontext := csr.io.mcontext
+  io.ifu.scontext := csr.io.scontext
 
   io.ifu.flush_icache := (0 until coreWidth).map { i =>
     (rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
@@ -1266,8 +1268,10 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
 
   // Connect breakpoint info to memaddrcalcunit
   for (i <- 0 until memWidth) {
-    mem_units(i).io.status := csr.io.status
-    mem_units(i).io.bp     := csr.io.bp
+    mem_units(i).io.status   := csr.io.status
+    mem_units(i).io.bp       := csr.io.bp
+    mem_units(i).io.mcontext := csr.io.mcontext
+    mem_units(i).io.scontext := csr.io.scontext
   }
 
   // LSU <> ROB
@@ -1383,7 +1387,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
   }
 
   // TODO: Does anyone want this debugging functionality?
-  val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen))
+  val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
   coreMonitorBundle := DontCare
   coreMonitorBundle.clock  := clock
   coreMonitorBundle.reset  := reset

src/main/scala/exu/execution-units/execution-unit.scala

@@ -131,6 +131,8 @@ abstract class ExecutionUnit(
     // only used by the mem unit
     val lsu_io = if (hasMem) Flipped(new boom.lsu.LSUExeIO) else null
     val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null
+    val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null
+    val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null
 
     // TODO move this out of ExecutionUnit
     val com_exception = if (hasMem || hasRocc) Input(Bool()) else null
@@ -380,6 +382,8 @@ class ALUExeUnit(
     maddrcalc.io.brupdate     <> io.brupdate
     maddrcalc.io.status     := io.status
     maddrcalc.io.bp         := io.bp
+    maddrcalc.io.mcontext   := io.mcontext
+    maddrcalc.io.scontext   := io.scontext
     maddrcalc.io.resp.ready := DontCare
     require(numBypassStages == 0)
 

src/main/scala/exu/execution-units/functional-unit.scala

@@ -184,6 +184,8 @@ abstract class FunctionalUnit(
 
     // only used by memaddr calc unit
     val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
+    val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
+    val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
 
   })
 }
@@ -511,10 +513,12 @@ class MemAddrCalcUnit(implicit p: Parameters)
     (size === 3.U && (effective_address(2,0) =/= 0.U))
 
   val bkptu = Module(new BreakpointUnit(nBreakpoints))
-  bkptu.io.status := io.status
-  bkptu.io.bp     := io.bp
-  bkptu.io.pc     := DontCare
-  bkptu.io.ea     := effective_address
+  bkptu.io.status   := io.status
+  bkptu.io.bp       := io.bp
+  bkptu.io.pc       := DontCare
+  bkptu.io.ea       := effective_address
+  bkptu.io.mcontext := io.mcontext
+  bkptu.io.scontext := io.scontext
 
   val ma_ld  = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
   val ma_st  = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned

src/main/scala/ifu/frontend.scala

@@ -13,7 +13,6 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.{withReset}
 import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.config._
@@ -268,6 +267,8 @@ class BoomFrontendIO(implicit p: Parameters) extends BoomBundle
   // Breakpoint info
   val status            = Output(new MStatus)
   val bp                = Output(Vec(nBreakpoints, new BP))
+  val mcontext          = Output(UInt(coreParams.mcontextWidth.W))
+  val scontext          = Output(UInt(coreParams.scontextWidth.W))
 
   val sfence = Valid(new SFenceReq)
 
@@ -335,7 +336,7 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
 
   val icache = outer.icache.module
   icache.io.invalidate := io.cpu.flush_icache
-  val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBEntries)))
+  val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays)))
   io.ptw <> tlb.io.ptw
   io.cpu.perf.tlbMiss := io.ptw.req.fire()
   io.cpu.perf.acquire := icache.io.perf.acquire
@@ -603,9 +604,11 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
 
       val valid = Wire(Bool())
       val bpu = Module(new BreakpointUnit(nBreakpoints))
-      bpu.io.status := io.cpu.status
-      bpu.io.bp     := io.cpu.bp
-      bpu.io.ea     := DontCare
+      bpu.io.status   := io.cpu.status
+      bpu.io.bp       := io.cpu.bp
+      bpu.io.ea       := DontCare
+      bpu.io.mcontext := io.cpu.mcontext
+      bpu.io.scontext := io.cpu.scontext
 
       val brsigs = Wire(new BranchDecodeSignals)
       if (w == 0) {

src/main/scala/ifu/icache.scala

@@ -13,6 +13,7 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.random._
 import chisel3.internal.sourceinfo.{SourceInfo}
 import chisel3.experimental.{chiselName}
 
@@ -44,7 +45,7 @@ class ICache(
   extends LazyModule
 {
   lazy val module = new ICacheModule(this)
-  val masterNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
+  val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
     name = s"Core ${staticIdForMetadataUseOnly} ICache")))))
 
@@ -63,7 +64,9 @@ class BoomICacheLogicalTreeNode(icache: ICache, deviceOpt: Option[SimpleDevice],
         dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes,
         dataECC = params.dataECC.map(OMECC.fromString),
         tagECC = params.tagECC.map(OMECC.fromString),
-        nTLBEntries = params.nTLBEntries,
+        nTLBEntries = params.nTLBSets * params.nTLBWays,
+        nTLBSets = params.nTLBSets,
+        nTLBWays = params.nTLBWays,
         maxTimSize = params.nSets * (params.nWays-1) * params.blockBytes,
         memories = icache.module.asInstanceOf[ICacheModule].dataArrays.map(_._2)
       )
@@ -172,7 +175,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   tl_out.d.ready := true.B
   require (edge_out.manager.minLatency > 0)
 
-  val repl_way = if (isDM) 0.U else LFSR16(refill_fire)(log2Ceil(nWays)-1,0)
+  val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0)
 
   val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W)))
   val tag_rdata = tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid)
@@ -371,7 +374,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     "Refill cycles : " + refillCycles,
     "RAMs          : (" +  wordBits/nBanks + " x " + nSets*refillCycles + ") using " + nBanks + " banks",
     "" + (if (nBanks == 2) "Dual-banked" else "Single-banked"),
-    "I-TLB entries : " + cacheParams.nTLBEntries + "\n")
+    "I-TLB ways    : " + cacheParams.nTLBWays + "\n")
 }
 
 

src/main/scala/lsu/dcache.scala

@@ -381,17 +381,17 @@ class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Paramet
   private val tileParams = p(TileKey)
   protected val cfg = tileParams.dcache.get
 
-  protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLClientParameters(
+  protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
     name          = s"Core ${staticIdForMetadataUseOnly} DCache",
     sourceId      = IdRange(0, 1 max (cfg.nMSHRs + 1)),
     supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
 
-  protected def mmioClientParameters = Seq(TLClientParameters(
+  protected def mmioClientParameters = Seq(TLMasterParameters.v1(
     name          = s"Core ${staticIdForMetadataUseOnly} DCache MMIO",
     sourceId      = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),
     requestFifo   = true))
 
-  val node = TLClientNode(Seq(TLClientPortParameters(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(
     cacheClientParameters ++ mmioClientParameters,
     minLatency = 1)))
 

src/main/scala/lsu/lsu.scala

@@ -247,7 +247,7 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
 
 
   val dtlb = Module(new NBDTLB(
-    instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBEntries)))
+    instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays)))
 
   io.ptw <> dtlb.io.ptw
   io.core.perf.tlbMiss := io.ptw.req.fire()

src/main/scala/lsu/tlb.scala

@@ -119,7 +119,7 @@ class NBDTLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge
   def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
 
   val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
-  val sectored_entries = Reg(Vec(cfg.nEntries / cfg.nSectors, new Entry(cfg.nSectors, false, false)))
+  val sectored_entries = Reg(Vec((cfg.nSets * cfg.nWays) / cfg.nSectors, new Entry(cfg.nSectors, false, false)))
   val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new Entry(1, true, true)))
   val special_entry = (!pageGranularityPMPs).option(Reg(new Entry(1, true, false)))
   def ordinary_entries = sectored_entries ++ superpage_entries

src/main/scala/util/util.scala

@@ -390,7 +390,7 @@ object MaskUpper
  */
 object Transpose
 {
-  def apply[T <: chisel3.core.Data](in: Vec[Vec[T]]) = {
+  def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
     val n = in(0).size
     VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
   }
@@ -417,7 +417,7 @@ object SelectFirstN
 /**
  * Connect the first k of n valid input interfaces to k output interfaces.
  */
-class Compactor[T <: chisel3.core.Data](n: Int, k: Int, gen: T) extends Module
+class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
 {
   require(n >= k)