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api/index.html

@@ -581,12 +581,12 @@
 
 <h1 id="risc-v-steel-api">RISC-V Steel API</h1>
 <p>RISC-V Steel API is a set of function calls to configure and control RISC-V Steel SoC IP, making it easier to develop applications for it.</p>
-<p>To start using the API in your application you must include the <code>rvsteel_api.h</code> header in your source code:</p>
-<div class="language-c highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="cp">#include</span><span class="w"> </span><span class="cpf">&quot;rvsteel_api.h&quot;</span>
+<p>To start using the API in your application you must include the <code>rvsteel-api.h</code> header in your source code:</p>
+<div class="language-c highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="cp">#include</span><span class="w"> </span><span class="cpf">&quot;rvsteel-api.h&quot;</span>
 </span><span id="__span-0-2"><a id="__codelineno-0-2" name="__codelineno-0-2" href="#__codelineno-0-2"></a>
 </span><span id="__span-0-3"><a id="__codelineno-0-3" name="__codelineno-0-3" href="#__codelineno-0-3"></a><span class="c1">// ... your code ...</span>
 </span></code></pre></div>
-<p>This header file is saved in the <code>sw/api/</code> folder along with its source code, <code>rvsteel_api.c</code>. The API is compiled and linked to your project by default if you use the template project (located in <code>sw/dev-template/</code>).</p>
+<p>This header file is saved in the <code>software-dev/rvsteel-api/</code> folder along with its source code, <code>rvsteel-api.c</code>. The API is compiled and linked to your project by default if you use the template project (located in <code>software-dev/template-project/</code>).</p>
 <p>The following sections contain detailed information about the available API calls.</p>
 <h2 id="uart-communication">UART communication</h2>
 <p class="api-call"><code class="language-c highlight"><span class="kt">void</span><span class="w"> </span><span class="nf">uart_send_char</span><span class="p">(</span><span class="k">const</span><span class="w"> </span><span class="kt">char</span><span class="w"> </span><span class="n">c</span><span class="p">);</span></code></p>

core/index.html

@@ -654,7 +654,7 @@ <h2 id="introduction">Introduction</h2>
 <p>RISC-V Steel Processor Core is a single-issue, in-order, unpipelined processor core.</p>
 <p>RISC-V Steel Processor Core can run real-time operating systems and bare-metal embedded software. It is designed to work as a processing unit in a wide variety of embedded applications.</p>
 <h2 id="source-files">Source files</h2>
-<p>RISC-V Steel Processor Core has a single source file, <code>rvsteel_core.v</code>, saved in the <code>hw/core/</code> folder.</p>
+<p>RISC-V Steel Processor Core has a single source file, <code>rvsteel_core.v</code>, saved in the <code>ip/core/</code> folder.</p>
 <h2 id="io-signals">I/O signals</h2>
 <p><strong id="table-1">Table 1</strong> - RISC-V Steel Processor Core input and output signals</p>
 <table>

getting-started/index.html

@@ -644,7 +644,7 @@ <h2 id="program-the-fpga">Program the FPGA</h2>
 </li>
 <li>
 <p>Search for <code>create-project-XXX.tcl</code> and click <strong>Ok</strong>. <code>XXX</code> stands for your board name.</p>
-<p>This file is located at <code>demos/XXX/</code>.</p>
+<p>This file is located at <code>hello-world/XXX/</code>.</p>
 <p>Running this script will create a new Vivado project for your FPGA board with the Hello World demo.</p>
 <p>To save your time, we provide a precompiled bitstream to program the FPGA in the same directory as the script.</p>
 <p>Generating the bitstream might be a bit slow. If you want to generate it anyway click <strong>Generate Bitstream</strong> in the <strong>Flow</strong> menu.</p>
@@ -666,8 +666,8 @@ <h2 id="program-the-fpga">Program the FPGA</h2>
 </li>
 <li>
 <p>Search for <code>hello_world_XXX.bit</code>.</p>
-<p>This file is located at <code>demos/XXX/</code>.</p>
-<p>In case you generated the bitstream yourself you can find it at <code>demos/XXX/hello-world-XXX/hello-world-XXX.runs/impl_1</code>.</p>
+<p>This file is located at <code>hello-world/XXX/</code>.</p>
+<p>In case you generated the bitstream yourself you can find it at <code>hello-world/XXX/hello-world-XXX/hello-world-XXX.runs/impl_1</code>.</p>
 </li>
 <li>
 <p>Click on <strong>Program</strong> and wait for Vivado to finish programming the FPGA.</p>

license/index.html

@@ -526,7 +526,7 @@ <h1 id="license">License</h1>
 <p>RISC-V Steel is free and open. It is distributed under the <a href="https://choosealicense.com/licenses/mit/">MIT License</a>, reproduced below.</p>
 <hr />
 <p><small></p>
-<p><strong>Copyright (c) 2020-2024 Rafael Calcada</strong></p>
+<p><strong>Copyright (c) 2020-present Rafael Calcada</strong></p>
 <p>Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:</p>
 <p><strong>The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.</strong></p>
 <p>THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</p>

soc/index.html

@@ -677,7 +677,7 @@
 
 <h1 id="risc-v-steel-system-on-chip-ip-reference-guide">RISC-V Steel System-on-Chip IP </br><small>Reference Guide</small></h1>
 <h2 id="introduction">Introduction</h2>
-<p>RISC-V Steel SoC IP is a system-on-chip design with RISC-V Steel Processor Core, RAM memory and UART module. It comes with an <a href="../api/">API for software development</a> that makes it easier for hardware engineers to develop and deploy RISC-V embedded applications.</p>
+<p>RISC-V Steel SoC IP is a system-on-chip design with RISC-V Steel Processor Core, RAM memory and UART module. It comes with an <a href="../software-guide/#soc-ip-api-reference">API for software development</a> that makes it easier for hardware engineers to develop and deploy RISC-V embedded applications.</p>
 <p>In this Reference Guide you find information on the SoC IP hardware design. See the <a href="../software-guide/">Software Guide</a> for instructions on how to write, compile and run software for the SoC IP.</p>
 <h2 id="design-overview">Design overview</h2>
 <p><strong id="figure-1">Figure 1</strong> - RISC-V Steel SoC IP design overview</p>
@@ -688,34 +688,40 @@ <h2 id="source-files">Source files</h2>
 <thead>
 <tr>
 <th>Module name</th>
-<th>Source file</th>
+<th>File</th>
+<th>Location</th>
 <th>Description</th>
 </tr>
 </thead>
 <tbody>
 <tr>
 <td><strong>rvsteel_soc</strong></td>
-<td><code>hw/soc/rvsteel_soc.v</code></td>
+<td><code>rvsteel_soc.v</code></td>
+<td><code>ip/soc/</code></td>
 <td>Top module of RISC-V Steel SoC IP</td>
 </tr>
 <tr>
 <td><strong>rvsteel_core</strong></td>
-<td><code>hw/core/rvsteel_core.v</code></td>
+<td><code>rvsteel_core.v</code></td>
+<td><code>ip/core/</code></td>
 <td>RISC-V Steel Processor Core</td>
 </tr>
 <tr>
-<td><strong>rvsteel_ram</strong></td>
-<td><code>hw/ram/rvsteel_ram.v</code></td>
+<td><strong>ram_memory</strong></td>
+<td><code>ram_memory.v</code></td>
+<td><code>ip/soc</code></td>
 <td>RAM memory</td>
 </tr>
 <tr>
-<td><strong>rvsteel_uart</strong></td>
-<td><code>hw/uart/rvsteel_uart.v</code></td>
+<td><strong>uart</strong></td>
+<td><code>uart.v</code></td>
+<td><code>ip/soc</code></td>
 <td>UART</td>
 </tr>
 <tr>
-<td><strong>rvsteel_bus</strong></td>
-<td><code>hw/bus/rvsteel_bus.v</code></td>
+<td><strong>system_bus</strong></td>
+<td><code>system_bus.v</code></td>
+<td><code>ip/soc</code></td>
 <td>System Bus</td>
 </tr>
 </tbody>

software-guide/index.html

@@ -630,7 +630,7 @@ <h4>4. Compile and install</h4>
 <h2 id="building-a-new-application">Building a new application</h2>
 <h4>1. Make a copy of the software development template project.</h4>
 
-<p>The template project is all you need to start and is located at <code>sw/dev-template/</code>.</p>
+<p>The template project is all you need to start and is located at <code>software-dev/template-project/</code>.</p>
 <h4>2. Edit the Makefile.</h4>
 
 <p>The template project comes with a Makefile to help you automate the tasks of compiling the software and generating a memory initialization file.</p>
@@ -643,7 +643,7 @@ <h4>2. Edit the Makefile.</h4>
 </span><span id="__span-7-6"><a id="__codelineno-7-6" name="__codelineno-7-6" href="#__codelineno-7-6"></a># Memory size (must be set to the same value of the MEMORY_SIZE parameter of rvsteel_soc module)
 </span><span id="__span-7-7"><a id="__codelineno-7-7" name="__codelineno-7-7" href="#__codelineno-7-7"></a>MEMORY_SIZE       ?= 8192
 </span><span id="__span-7-8"><a id="__codelineno-7-8" name="__codelineno-7-8" href="#__codelineno-7-8"></a># Path to RISC-V Steel API
-</span><span id="__span-7-9"><a id="__codelineno-7-9" name="__codelineno-7-9" href="#__codelineno-7-9"></a>RVSTEEL_API_DIR   ?= ../api
+</span><span id="__span-7-9"><a id="__codelineno-7-9" name="__codelineno-7-9" href="#__codelineno-7-9"></a>RVSTEEL_API_DIR   ?= ../rvsteel-api
 </span><span id="__span-7-10"><a id="__codelineno-7-10" name="__codelineno-7-10" href="#__codelineno-7-10"></a># The full path to RISC-V GNU Toolchain binaries in this machine + RISC-V binaries prefix
 </span><span id="__span-7-11"><a id="__codelineno-7-11" name="__codelineno-7-11" href="#__codelineno-7-11"></a>RISCV_PREFIX      ?= /opt/riscv/bin/riscv32-unknown-elf-
 </span></code></pre></div>
@@ -673,7 +673,7 @@ <h2 id="running-the-application">Running the application</h2>
 <h4>1. Specify the path to the memory initialization file</h4>
 
 <p>The SoC IP has a parameter called <code>MEMORY_INIT_FILE</code> that can be set when instantiating its top module. If you specify this parameter the RAM memory will be initialized with the contents of the memory file that you provided. </p>
-<p>In the example below (that you can find at <code>demos/arty-a7/hello-world-arty-a7.v</code>) an instance of the SoC IP for the <a href="https://digilent.com/reference/programmable-logic/arty-a7/reference-manual">Digilent Arty-A7 FPGA board</a> is configured to load a Hello World program:</p>
+<p>In the example below (that you can find at <code>hello-world/arty-a7/hello-world-arty-a7.v</code>) an instance of the SoC IP for the <a href="https://digilent.com/reference/programmable-logic/arty-a7/reference-manual">Digilent Arty-A7 FPGA board</a> is configured to load a Hello World program:</p>
 <div class="language-verilog highlight"><pre><span></span><code><span id="__span-9-1"><a id="__codelineno-9-1" name="__codelineno-9-1" href="#__codelineno-9-1"></a><span class="n">rvsteel_soc</span><span class="w">                  </span><span class="p">#(</span>
 </span><span id="__span-9-2"><a id="__codelineno-9-2" name="__codelineno-9-2" href="#__codelineno-9-2"></a><span class="w">    </span><span class="p">.</span><span class="n">CLOCK_FREQUENCY</span><span class="w">          </span><span class="p">(</span><span class="mh">50000000</span><span class="w">           </span><span class="p">),</span>
 </span><span id="__span-9-3"><a id="__codelineno-9-3" name="__codelineno-9-3" href="#__codelineno-9-3"></a><span class="w">    </span><span class="p">.</span><span class="n">UART_BAUD_RATE</span><span class="w">           </span><span class="p">(</span><span class="mh">9600</span><span class="w">               </span><span class="p">),</span>