RISC-V Steel - v1.1

What's New

This version of RISC-V Steel adds the following features to the Processor Core IP:

• 16 Fast Interrupt lines
• Processor Core IP Simulator

The following features were added to the System-on-Chip IP:

• System-on-Chip IP Simulator

This version also includes a refactoring of the system bus module aimed to make it easier to integrate devices in the SoC IP and a new timer module (yet to be integrated in the SoC).

Bug Fixes

• Fix the priority order of machine timer and software interrupts in the Processor Core IP

What's Changed

• Fix: Use I_OR_E to select TRAP_ADDRESS by @AlexxMarkov in #6
• Updated regfile to reset properly by @Aidan-McNay in #9
• Adding example for FPGA tang Nano 20k by @JN513 in #11
• Updating implementation for the tang nano 20k example by @JN513 in #12
• A short refactoring without changing behavior by @AlexxMarkov in #16
• Example of launching RISC-V Steel using Verilator by @AlexxMarkov in #17
• Ref: Small optimization of the core simulation shell, generation *.fst by @AlexxMarkov in #18
• Short refactoring + dump comparison script by @AlexxMarkov in #19
• New test script functionality, system bus by @AlexxMarkov in #20
• Machine Timer Registers (mtime and mtimecmp) and control registers by @AlexxMarkov in #29
• Doc page update by @rafaelcalcada in #30
• Create CONTRIBUTING.md by @rafaelcalcada in #31
• Rename folders, reorganize files by @rafaelcalcada in #33
• Extending rvsteel-api to rvsteel-soc by @AlexxMarkov in #32
• Create local gitignore files and remove the global one. by @riscv-steel in #34
• Use riscv32-unknown-elf-objcopy to generate Verilog memory init files instead of octal dump (od) by @rafaelcalcada in #35
• Fix loading mem init files in the new format in the Core IP simulator by @rafaelcalcada in #36
• Add --quiet option to Core IP simulator by @rafaelcalcada in #37
• Update unit tests by @rafaelcalcada in #38
• Added log-out and log-level options to Core IP simulator by @AlexxMarkov in #39
• Added SoC IP Simulation by @AlexxMarkov in #40
• Small refactoring Core and SoC Simulation by @AlexxMarkov in #41
• Added fast IRQ (extension CSR regs mie and mip) by @AlexxMarkov in #42
• Prepare a new release for the Fast IRQ feature by @rafaelcalcada in #43

New Contributors

• @AlexxMarkov made their first contribution in #6
• @Aidan-McNay made their first contribution in #9
• @JN513 made their first contribution in #11
• @riscv-steel made their first contribution in #34

Full Changelog: https://github.com/riscv-steel/riscv-steel/commits/v1.1

v1.0 - First release!

The first release of RISC-V Steel includes:

• Processor Core IP (RV32I + Zicsr extension + M-mode privileged architecture)
• SoC IP (Processor Core IP + UART + Memory)
• API and template project for software development
• Documentation website (https://riscv-steel.github.io/riscv-steel/)

Minor changes in version 1 will not change the interface of the available IPs and will keep backward compatibility. The same applies to the software API.

Full Changelog: https://github.com/riscv-steel/riscv-steel/commits/v1.0