Further textual cleaning.

riscv · Jun 29, 2023 · 220dcf3 · 220dcf3
1 parent 1d22c43
commit 220dcf3
Show file tree

Hide file tree

Showing 3 changed files with 12 additions and 14 deletions.
diff --git a/doc/insns/fcvt_BF16_S.adoc b/doc/insns/fcvt_BF16_S.adoc
@@ -38,10 +38,9 @@ a new encoding is used in bits 24:20.
 Description::
 Narrowing convert FP32 value to a BF16 value. Round according to the RM field.
 
-This new floating-point-to-floating-point conversion instruction is defined analogously to the
-pre-existing floating-point-to-floating-point conversion instructions.
+This instruction is similar to other narrowing
+floating-point-to-floating-point conversion instructions.
 
-The result is NaN-boxed by writing all of the most significant `FLEN`-16 bits with 1s.
 
 Exceptions:  Overflow, Underflow, Inexact, Invalid
 

diff --git a/doc/insns/fcvt_S_BF16.adoc b/doc/insns/fcvt_S_BF16.adoc
@@ -34,22 +34,21 @@ used in bits 24:20 to indicate that the source is BF16.
 Description:: 
 Converts a BF16 value to an FP32 value. The conversion is exact.
 
-This new floating-point-to-floating-point conversion instruction is defined analogously to the
-pre-existing floating-point-to-floating-point conversion instructions.
+This instruction is similar to other widening
+floating-point-to-floating-point conversion instructions.
 
-If the input is normal or infinity, the BF16 encoded value is shifted to the left by 16 places and the
+[NOTE]
+====
+If the input is normal or infinity, the BF16 encoded value is shifted 
+to the left by 16 places and the
 least significant 16 bits are written with 0s.
-If the input is a NaN, the canonical NaN is returned. Furthermore, if the input is a signalling NaN,
-the invalid flag is rasied. 
-
 
 The result is NaN-boxed by writing the most significant `FLEN`-32 bits with 1s.
+====
+
 
-Exceptions: Invalid
 
-// Operation::
-// --
-// --
+Exceptions: Invalid
 
 Included in: <<zfbfmin>>
 

diff --git a/doc/insns/vfwmaccbf16.adoc b/doc/insns/vfwmaccbf16.adoc
@@ -59,7 +59,7 @@ Description::
 This instruction performs a widening fused multiply-accumulate
 operation, where each pair of BF16 values are multiplied and their
 unrounded product is added to the corresponding FP32 accumulate value.
-The sum is rounded to FP32 using the dynamic rounding mode in `frm`.
+The sum is rounded according to the _frm_ register.
 
 
 In the vector-vector version, the BF16 elements are read from `vs1`