Changes from public review

Fixed dependencies for Zvfbfmin.
Clarified language on widening convert.
Fixed typos.

doc/insns/vfwcvtbf16_f_f_v.adoc

@@ -40,18 +40,16 @@ Arguments::
 Description:: 
 Widening convert from BF16 to FP32. The conversion is exact.
 
-This instruction is similar to `vfwcvt.f.f.v` - Convert single-width float to double-width float.
-However, the single-width float is limited to the BF16 format.
+This instruction is similar to `vfwcvt.f.f.v` which converts a
+floating-point value in a narrower format into a wider format.
+However, here the narrower format is limited to BF16.
 
 [NOTE]
 ====
 If the input is normal or infinity, the BF16 encoded value is shifted 
 to the left by 16 places and the
 least significant 16 bits are written with 0s.
 ====
-// If the input is a NaN, the canonical NaN is returned. Furthermore,
-// if the input is a signalling NaN,
-// the invalid flag is rasied.
 
 Exceptions: Invalid
 

doc/riscv-bfloat16-extensions.adoc

@@ -18,8 +18,11 @@ The BF16 extensions defined in this specification (i.e., `Zfbfmin`,
 `F`. Furthermore, the vector BF16 extensions (i.e.,`Zvfbfmin`, and
 `Zvfbfwma`) depend on the `"V"` Vector Extension for Application
 Processors or the `Zve32f` Vector Extension for Embedded Processors.
-Finally there exist dependencies between the newly defined extensions:
-`Zvfbfmin` depends on `Zfbfmin` and `Zvfbfwma` depends on `Zvfbfmin`.
+
+As stated later in this specification, 
+there exists a dependency between the newly defined extensions:
+`Zvfbfwma` depends on `Zfbfmin`
+and `Zvfbfmin`.
 
 This initial set of BF16 extensions provides very basic functionality
 including  scalar and vector conversion between BF16 and
@@ -28,6 +31,5 @@ instructions.
 
 
 include::riscv-bfloat16-zfbfmin.adoc[]
-// include::riscv-bfloat16-zfbfinxmin.adoc[]
 include::riscv-bfloat16-zvfbfmin.adoc[]
 include::riscv-bfloat16-zvfbfwma.adoc[]

doc/riscv-bfloat16-zfbfmin.adoc

@@ -5,10 +5,6 @@ This extension provides the minimal set of instructions needed to enable scalar
 of the BF16 format. It enables BF16 as an interchange format as it provides conversion
 between BF16 values and FP32 values. 
 
-// This extension includes the `FLH`, `FSH`, `FMV.X.H`, and `FMV.H.X` instructions
-// that are defined in the `Zfh` spec. That said, this extension does not require
-// nor depend on the implementation of the `Zfh` or `Zfhmin` extensions.
-
 This extension requires the single-precision floating-point extension
 `F`, and the `FLH`, `FSH`, `FMV.X.H`, and `FMV.H.X` instructions as
 defined in the `Zfh` extension.
@@ -21,13 +17,13 @@ These extensions are intended to support the case where BF16 values are used as
 precision versions of FP32 values, where use of BF16 provides a two-fold advantage for
 storage, bandwidth, and computation. In this use case, the BF16 values are typcially 
 multiplied by each other and accumulated into FP32 sums. 
-These sums are typcially converted to BF16
+These sums are typically converted to BF16
 and then used as subsequent inputs. The operations on the BF16 values can be performed
-on the CPU or a loosly coupled coprocessor.
+on the CPU or a loosely coupled coprocessor.
 
 Subsequent extensions might provide support for native BF16 arithmetic. Such extensions
 could add additional conversion
-instructions to allow all suported formats to be converted to and from BF16.  
+instructions to allow all supported formats to be converted to and from BF16.  
 ====
 
 [NOTE]

doc/riscv-bfloat16-zvfbfmin.adoc

@@ -5,7 +5,7 @@ This extension provides the minimal set of instructions needed to enable vector
 format. It enables BF16 as an interchange format as it provides conversion between BF16 values
 and FP32 values.
 
-This extension requires the `Zfbfmin` extension and either the
+This extension requires either the
 "V" extension or the `Zve32f` embedded vector extension.
 
 [NOTE]
@@ -14,15 +14,15 @@ While conversion instructions tend to include all supported formats, in these ex
 only support conversion between BF16 and FP32 as we are targeting a special use case.
 These extensions are intended to support the case where BF16 values are used as reduced
 precision versions of FP32 values, where use of BF16 provides a two-fold advantage for
-storage, bandwidth, and computation. In this use case, the BF16 values are typcially 
+storage, bandwidth, and computation. In this use case, the BF16 values are typically 
 multiplied by each other and accumulated into FP32 sums. 
-These sums are typcially converted to BF16
+These sums are typically converted to BF16
 and then used as subsequent inputs. The operations on the BF16 values can be performed
-on the CPU or a loosly coupled coprocessor.
+on the CPU or a loosely coupled coprocessor.
 
 Subsequent extensions might provide support for native BF16 arithmetic. Such extensions
 could add additional conversion
-instructions to allow all suported formats to be converted to and from BF16.  
+instructions to allow all supported formats to be converted to and from BF16.  
 ====
 
 [NOTE]
@@ -35,7 +35,7 @@ on some inputs for the RNE and RMM rounding modes.
 
 Likewise, exact conversions from BF16 to larger precisions can be synthesized by first
 converting to FP32 and then converting from FP32 to the target precision. Conversions
-from larger precisions coud be synthesized by first converting to FP32 and then
+from larger precisions could be synthesized by first converting to FP32 and then
 converting from FP32 to BF16. As with the arithmetic instructions described above,
 this method of converting values to BF16 can be off by by 1-ulp 
 on some inputs for the RNE and RMM rounding modes.

doc/riscv-bfloat16-zvfbfwma.adoc

@@ -4,8 +4,7 @@
 This extension provides
 a vector widening BF16 mul-add instruction that accumulates into FP32. 
 
-// This extension depends on the "V" extension or the `Zve32f` embedded vector extension.
-This extension requires the `Zvfbfmin` extension.
+This extension requires the `Zvfbfmin` extension and the `Zfbfmin` extension.
 
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