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AR: Remove Message Registers.
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These were first introduced in #728.

Hopefully I got everything.
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timsifive committed Sep 28, 2023
1 parent 0b80f88 commit 1aab674
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43 changes: 4 additions & 39 deletions debug_module.tex
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Expand Up @@ -311,41 +311,6 @@ \section{Halt Groups, Resume Groups, and External Triggers} \label{hrgroups}
explicitly allowed. In that case it must be possible to discover the groups by
using \RdmDmcsTwo even if it's not possible to change the configuration.

\section{Message Registers}
\label{sec:mr}

Message Registers (MRs) are registers that implement fewer features than a
traditional register. They support just enough features to pass messages back
and forth.

Only registers whose description explicitly says they may be MRs may be
implemented as MRs instead of traditional registers. \RdmDataZero through
\RdmDataEleven may be MRs, used to let the debugger pass arguments to abstract
commands, and let the DM pass results from abstract commands back. Debuggers
must not assume that they'll be able to read back a value that they wrote to a
register that may be an MR.

A traditional dual-ported register contains a single value, which can be
read/written through both ports. A MR has two ports: PortA and PortB. It
contains two values: ValueA and ValueB. Only one of these values has defined
contents at any one time.

\begin{steps}{For an MR:}
\item A write to PortA updates ValueA with the written value, and makes
ValueB \unspecified.
\item A write to PortB updates ValueB with the written value, and makes
ValueA \unspecified.
\item A read from PortA returns ValueB.
\item A read from PortB returns ValueA.
\end{steps}

\begin{commentary}
A regular register can be used to implement an MR. In some FPGAs it is
cheaper to trade off storage for muxes, and in that case the storage can be
duplicated (one set of bits for sending and one for receiving) to avoid
having to implement muxes to read/write data from/to the correct side.
\end{commentary}

\section{Abstract Commands} \label{abstractcommands}

The DM supports a set of abstract commands, most of which
Expand Down Expand Up @@ -375,12 +340,12 @@ \section{Abstract Commands} \label{abstractcommands}
unavailable, or because they encounter an error during execution.

If the command takes arguments, the debugger
must write them to the {\tt data} MRs before writing to \RdmCommand. If a
must write them to the {\tt data} registers before writing to \RdmCommand. If a
command returns results, the Debug Module must ensure they are placed
in the {\tt data} MRs before \FdmAbstractcsBusy is cleared.
Which {\tt data} MRs are used for the arguments is
in the {\tt data} registers before \FdmAbstractcsBusy is cleared.
Which {\tt data} registers are used for the arguments is
described in Table~\ref{tab:datareg}. In all cases the least-significant word
is placed in the lowest-numbered {\tt data} MR. The argument width
is placed in the lowest-numbered {\tt data} register. The argument width
depends on the command being executed, and is DXLEN where not explicitly
specified.

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7 changes: 1 addition & 6 deletions introduction.tex
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Expand Up @@ -67,8 +67,6 @@ \section{Terminology}
\item[Minimal RISC-V Debug Specification]
A subset of the full Debug Specification that allows for very small
implementations. See Chapter~\ref{chap:dm}.
\item[MR]
Message Register, described in Section~\ref{sec:mr}.
\item[NAPOT]
Naturally Aligned Power-Of-Two.
\item[NMI]
Expand Down Expand Up @@ -216,10 +214,7 @@ \subsubsection{Incompatible Changes During 1.0 Stable}
called 1.0 stable.}
\item \FcsrItriggerNmi was moved from \RcsrEtrigger to \RcsrItrigger, and is now
subject to the mode bits in that trigger.
\item DM {\tt data} registers are now Message Registers (see
Section~\ref{sec:mr}). Debuggers must not assume they can read back the same
value that they wrote, and must not assume that the result of the last abstract
command is available as argument to the next abstract command. \PR{728}
\item \PR{728} introduced Message Registers, which were later removed in \PR{878}.
\item It may not be possible to read the contents of the Program Buffer using
the {\tt progbuf} registers. \PR{731}
\end{steps}
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4 changes: 0 additions & 4 deletions xml/abstract_commands.xml
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Expand Up @@ -258,10 +258,6 @@
{\tt arg1} (which contains the address used) by the number of bytes
encoded in \FacAccessmemoryAamsize.

Implementations that allow this bit to be 1 must implement the
relevant {\tt data} registers as traditional registers instead of
MRs.

Supporting this variant is optional, but highly recommended for
performance reasons.
</field>
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6 changes: 1 addition & 5 deletions xml/dm_registers.xml
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Expand Up @@ -394,9 +394,6 @@
If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map
dedicated to shadowing the {\tt data} registers.

If this value is non-zero, then the {tt data} registers must be
traditional registers and not MRs.

Since there are at most 12 {\tt data} registers, the value in this
register must be 12 or smaller.
</field>
Expand Down Expand Up @@ -640,8 +637,7 @@
</register>

<register name="Abstract Data 0" short="data0" address="0x04">
\RdmDataZero through \RdmDataEleven may be Message Registers, whose
behavior is described in Section~\ref{sec:mr}. These registers may
\RdmDataZero through \RdmDataEleven are registers that may
be read or changed by abstract commands. \FdmAbstractcsDatacount indicates how many
of them are implemented, starting at \RdmDataZero, counting up.
Table~\ref{tab:datareg} shows how abstract commands use these
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