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Add support for Smdbltrp. #998

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merged 5 commits into from May 1, 2024
Merged

Add support for Smdbltrp. #998

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838d1e5
Add extcause field.
rtwfroody Apr 1, 2024
f798dca
Move extcause, and don't reserve any values.
rtwfroody Apr 1, 2024
099dc96
Add dcsr.cetrig for Smdbltrp
rtwfroody Apr 15, 2024
b8c29c9
Add critical error value to extcause
rtwfroody Apr 18, 2024
75e1d26
Rephrase critical error value; expand cetrig note
rtwfroody Apr 24, 2024
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52 changes: 50 additions & 2 deletions xml/core_registers.xml
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Expand Up @@ -70,7 +70,52 @@ same project unless stated otherwise.
available version of this spec.
</value>
</field>
<field name="0" bits="27:18" access="R" reset="0" />
<field name="0" bits="27" access="R" reset="0" />
<field name="extcause" bits="26:24" access="R" reset="0">
When {dcsr-cause} is 7, this optional field contains the value of a
more specific halt reason than "other." Otherwise it contains 0.

<value v="0" name="critical error">
The hart entered a critical error state, as defined in the
((Smdbltrp)) extension.
</value>

All other values are reserved for future versions of this spec, or
for use by other RISC-V extensions.
</field>
<field name="0" bits="23:20" access="R" reset="0" />
<field name="cetrig" bits="19" access="R/W" reset="0">
This bit is part of ((Smdbltrp)) and only exists when that extension
is implemented.

<value v="0" name="disabled">
A hart in a critical error state does not enter Debug Mode but
instead asserts the critical-error signal to the platform.
</value>

<value v="1" name="enabled">
A hart in a critical error state enters Debug Mode instead of
asserting the critical-error signal to the platform. Upon such
entry into Debug Mode, the cause field is set to 7, and the
extcause field is set to 0, indicating a critical error
triggered the Debug Mode entry. This cause has the highest
priority among all reasons for entering Debug Mode. Resuming
from Debug Mode following an entry from the critical error state
returns the hart to the critical error state.
</value>

[NOTE]
====
When {dcsr-cetrig} is 1, resuming from Debug Mode
following an entry due to a critical error will result in an
immediate re-entry into Debug Mode due to the critical error.
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The debugger may resume with cetrig set to 0 to allow the platform defined actions on critical-error signal to occur. Other possible actions include initiating a hart or platform reset using the Debug Module reset control.

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Adding this.

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Thanks!

The debugger may resume with {dcsr-cetrig} set to 0 to allow the
platform defined actions on critical-error signal to occur.
Other possible actions include initiating a hart or platform
reset using the Debug Module reset control.
====
</field>
<field name="0" bits="18" access="R" reset="0" />
<field name="ebreakvs" bits="17" access="WARL" reset="0">
<value v="0" name="exception">
`ebreak` instructions in VS-mode behave as described in the
Expand Down Expand Up @@ -212,7 +257,10 @@ same project unless stated otherwise.
Harts may report 3 for this cause instead.
</value>

Other values are reserved for future use.
<value v="7" name="other">
The hart halted for a reason other than the ones mentioned above.
{dcsr-extcause} may contain a more specific reason.
</value>
</field>
<field name="v" bits="5" access="WARL" reset="0">
Extends the prv field with the virtualization mode the hart was operating
Expand Down