Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Adding *tval address explanation text. #1319

Merged
merged 2 commits into from Apr 5, 2024
Merged

Adding *tval address explanation text. #1319

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c7ce7b3
Adding *tval address explanation text.
wmat Apr 4, 2024
0cff842
Change a physical address to any.
wmat Apr 5, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
4 changes: 3 additions & 1 deletion src/cmo.adoc
View file
Open in desktop
Expand Up @@ -89,7 +89,7 @@ a cache that first performs a read transfer from memory._

Caches organize copies of data into _cache blocks_, each of which represents a
contiguous, naturally aligned power-of-two (or _NAPOT_) range of memory
locations. A cache block is identified by a physical address corresponding to
locations. A cache block is identified by any of the physical addresses corresponding to
the underlying memory locations. The capacity and organization of a cache and
the size of a cache block are both _implementation-specific_, and the execution
environment provides software a means to discover information about the caches
Expand Down Expand Up @@ -381,6 +381,8 @@ exceptions and shall not access any caches or memory. During address
translation, the instruction does _not_ check the accessed and dirty bits and
neither raises an exception nor sets the bits.

When a page fault, guest-page fault, or access fault exception is taken, the relevant *tval CSR is written with the faulting effective address (i.e. the same faulting address value as for other causes of these exceptions).

[NOTE]
====
_Like a load or store instruction, a CMO instruction may or may not be permitted
Expand Down