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Add special_function for ADD and SUB relocations. #98
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ChangeLog: * New RISC-V GDB port
The symbol address in .eh_frame may be adjusted in _bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert a relocation whose addend symbol is in .eh_frame. Othrewise, the value may be adjusted twice. bfd/ChangeLog 2017-06-08 Kuan-Lin Chen <rufus@andestech.com> * elfnn-riscv.c (perform_relocation): Support the new R_RISCV_32_PCREL relocation. (riscv_elf_relocate_section): Likewise. * elfxx-riscv.c (howto_table): Likewise. (riscv_reloc_map): Likewise. * bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation. * libbfd.h: Regenerate. gas/ChangeLog 2017-06-08 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a R_RISCV_32_PCREL relocation. include/ChangeLog 2017-06-08 Kuan-Lin Chen <rufus@andestech.com> * elf/riscv.h (R_RISCV_32_PCREL): New.
We currently delete bytes by shifting an entire BFD backwards to overwrite the bytes we no longer need. The result is that relaxing a BFD is quadratic time. This patch adds an additional relocation that specifies a byte range that will be deleted from the final object file, and adds a relaxation pass (between the existing passes that delete bytes and the alignment pass) that actually deletes the bytes. Note that deletion is still quadratic time, and nothing uses R_RISCV_DELETE yet. R_RISCV_DELETE will never be emitted into ELF objects, so therefor isn't exposed to the rest of binutils.
In the medany code model the compiler generates PCREL_HI20+PCREL_LO12 relocation pairs against local symbols because HI20+LO12 relocations can't reach high addresses. We relax HI20+LO12 pairs to GPREL relocations when possible, which is an important optimization for Dhrystone. Without this commit we are unable to relax PCREL_HI20+PCREL_LO12 pairs to GPREL when possible, causing a XX% permormance hit on Dhrystone on Rocket. Note that we'll now relax la gp, __global_pointer$ to mv gp, gp which probably isn't what you want in your entry code. Users who want gp-relative symbols to continue to resolve should add ".option norelax" accordingly. Due to this, the assembler now pairs PCREL relocations with RELAX relocations when they're expected to be relaxed.
The dynrelro introduction wasn't implemented quite right for RISC-V, as it didn't consider TLS copy relocs.
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I think there is an alternative for this special reloc function, because one could just use the generic reloc function for at least R_RISCV_ADD8, R_RISCV_ADD16, R_RISCV_ADD32, R_RISCV_ADD64, R_RISCV_SUB16 and R_RISCV_SUB32. When you set the src_mask in the HOWTO to MINUS_ONE, the addition will be done also with bfd_elf_generic_reloc. For subtraction one can use the special sizes -1 and -2. So this works at least for SUB16 and SUB32. Checkout https://github.com/riscv/riscv-binutils-gdb/blob/riscv-next/bfd/reloc.c#L891 |
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I think R_RISCV_ADDXX relocations can use generic reloc function if they do not use the value in the section content. (As far as I know, these relocations seems do not use so far.) |
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This was merged here e9900b6 |
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For issue-248 to print the correct line number.
For issue-81 to make GCC generate the human readable cfi directive.