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1. Zc* v1.0.4-2

1.1. Change history since v0.70.1 (tagged release)

Table 1. Change history
Version change

v1.0.4-3

Added misa.C clarification

v1.0.4-2

Added rule that C implies Zca, Zcf, Zcd - discussed in riscv/riscv-isa-manual#1132

v1.0.4-1

Added rule that Zcf implies F and Zcd implies D - discussed in #221

v1.0.4

Resolve #221 - Zcf doesn’t exist on RV64 as it contains no instructions

v1.0.3-1

Replace statement about non-idempotent memory handler completing the sequence (non-normative)

v1.0.3

Add definition of Zce

v1.0.2

Fix Architecture Review Committee feedback on instruction formats

v1.0.1

Post public review fixes: Add instruction formats (issue 192). Clarify that Zcmt/Zcmp are for embedded CPUs (issue 190). Fix some typos.

v1.0.0-RC5.7

Add Zcb description and fix some typos. PUBLIC REVIEW REVISION.

v1.0.0-RC5.6

Remove Zcmpe which is not frozen and is causing confusion

v1.0.0-RC5.5

Following ARC review Adjust the split so we have 224 cm.jalt and 32 cm.jt

v1.0.0-RC5.4

Change wording for dependencies to match arch manual "Zxxx requires Zyyy" changed to "Zxxx depends on Zyyy"

v1.0.0-RC5.3

Add dependency on Zicsr for Zcmt

v1.0.0-RC5.2

Adjust the split so we have 240 cm.jalt and 16 cm.jt

v1.0.0-RC5.1

Make cm.jt/cm.jalt only valid if JVT.mode=0, and allow different behaviour in the future if JVT.mode>0

v1.0.0-RC5

Revert to cm.jt and cm.jalt encodings, to avoid toolchain and trace problems

v1.0.0-RC4.1

Resolve typographical issues with the document only, no actual changes

v1.0.0-RC4

Release candidate

Remove Zcmb as benefit is low. Remove cm.jalt, read LSB of jump table entry to determine whether to link

v0.70.5

Resolve #163 - jvt.base is WARL and fewer bits than the max can be implemented

v0.70.4

Clarified #159 - Need Zbb and Zba for RV64 and M/ZMmul to get all of Zcb

Resolved #161

Resolved #160 - Allocated Smstateen bit 2 and added the relevant text

v0.70.3

Added rule that Zcf and Zcmt imply Zca (this text was missing, this is not a spec change: #151)

Added that Zcf is illegal for RV64, as it contains no instructions (clarification: #149)

Added push/pop examples in the push/pop section

v0.70.2

Stylistic changes only, removing redundant text.

Corrected field names on JVT CSR diagram, and fixed synopsis for cm.mvsa01

1.2. Zc* Overview

This document is in the ratified state. No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised.

Zc* is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encodings.

Zcm* all reuse the encodings for c.fld, c.fsd, c.fldsp, c.fsdsp.

Table 2. Zc* extension overview
Instruction Zca Zcf Zcd Zcb Zcmp Zcmt

The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores

C excl. c.f*

yes

The Zcf extension is added as a way to refer to compressed single-precision floating-point load/stores

c.flw

rv32

c.flwsp

rv32

c.fsw

rv32

c.fswsp

rv32

The Zcd extension is added as a way to refer to compressed double-precision floating-point load/stores

c.fld

yes

c.fldsp

yes

c.fsd

yes

c.fsdsp

yes

Simple operations for use on all architectures

c.lbu

yes

c.lh

yes

c.lhu

yes

c.sb

yes

c.sh

yes

c.zext.b

yes

c.sext.b

yes

c.zext.h

yes

c.sext.h

yes

c.zext.w

yes

c.mul

yes

c.not

yes

PUSH/POP and double move which overlap with c.fsdsp. Complex operations intended for embedded CPUs

cm.push

yes

cm.pop

yes

cm.popret

yes

cm.popretz

yes

cm.mva01s

yes

cm.mvsa01

yes

Table jump which overlaps with c.fsdsp. Complex operations intended for embedded CPUs

cm.jt

yes

cm.jalt

yes

1.3. C

The C extension is the superset of the following extensions:

  • Zca

  • Zcf if F is specified (RV32 only)

  • Zcd if D is specified

As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:

  • C always implies Zca

  • C+F implies Zcf (RV32 only)

  • C+D implies Zcd

1.4. Zce

The Zce extension is intended to be used for microcontrollers, and includes all relevant Zc extensions.

  • Specifying Zce on RV32 without F includes Zca, Zcb, Zcmp, Zcmt

  • Specifying Zce on RV32 with F includes Zca, Zcb, Zcmp, Zcmt and Zcf

  • Specifying Zce on RV64 always includes Zca, Zcb, Zcmp, Zcmt

    • Zcf doesn’t exist for RV64

Therefore common ISA strings can be updated as follows to include the relevant Zc extensions, for example:

  • RV32IMC becomes RV32IM_Zce

  • RV32IMCF becomes RV32IMF_Zce

1.5. MISA.C

MISA.C is set if the following extensions are selected:

  • Zca and not F

  • Zca, Zcf and F is specified (RV32 only)

  • Zca, Zcf and Zcd if D is specified (RV32 only)

    • this configuration excludes Zcmp, Zcmt

  • Zca, Zcd if D is specified (RV64 only)

    • this configuration excludes Zcmp, Zcmt

1.6. Zca

The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores.

Therefore it excluded all 16-bit floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp, c.fld, c.fldsp, c.fsd, c.fsdsp.

Note
 the C extension only includes F/D instructions when D and F are also specified

1.7. Zcf (RV32 only)

Zcf is the existing set of compressed single precision floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp.

Zcf is only relevant to RV32, it cannot be specified for RV64.

The Zcf extension depends on the Zca and F extensions.

1.8. Zcd

Zcd is the existing set of compressed double precision floating point loads and stores: c.fld, c.fldsp, c.fsd, c.fsdsp.

The Zcd extension depends on the Zca and D extensions.

1.9. Zcb

Zcb has simple code-size saving instructions which are easy to implement on all CPUs.

All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.

Note
 Zcb can be implemented on any CPU as the instructions are 16-bit versions of existing 32-bit instructions from the application class profile.

The Zcb extension depends on the Zca extension.

As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented.

The c.mul encoding uses the CA register format along with other instructions such as c.sub, c.xor etc.

Note
 c.sext.w is a pseudo-instruction for c.addiw rd, 0 (RV64)
RV32 RV64 Mnemonic Instruction

yes

yes

c.lbu rd', uimm(rs1')

[insns-c_lbu]

yes

yes

c.lhu rd', uimm(rs1')

[insns-c_lhu]

yes

yes

c.lh rd', uimm(rs1')

[insns-c_lh]

yes

yes

c.sb rs2', uimm(rs1')

[insns-c_sb]

yes

yes

c.sh rs2', uimm(rs1')

[insns-c_sh]

yes

yes

c.zext.b rsd'

[insns-c_zext_b]

yes

yes

c.sext.b rsd'

[insns-c_sext_b]

yes

yes

c.zext.h rsd'

[insns-c_zext_h]

yes

yes

c.sext.h rsd'

[insns-c_sext_h]

yes

c.zext.w rsd'

[insns-c_zext_w]

yes

yes

c.not rsd'

[insns-c_not]

yes

yes

c.mul rsd', rs2'

[insns-c_mul]

1.10. Zcmp

The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

Note
 Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.

The Zcmp extension depends on the Zca extension.

The PUSH/POP assembly syntax uses several variables, the meaning of which are:

  • reg_list is a list containing 1 to 13 registers (ra and 0 to 12 s registers)

    • valid values: {ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, …​, {ra, s0-s8}, {ra, s0-s9}, {ra, s0-s11}

    • note that {ra, s0-s10} is not valid, giving 12 lists not 13 for better encoding

  • stack_adj is the total size of the stack frame.

    • valid values vary with register list length and the specific encoding, see the instruction pages for details.

RV32 RV64 Mnemonic Instruction

yes

yes

cm.push {reg_list}, -stack_adj

[insns-cm_push]

yes

yes

cm.pop {reg_list}, stack_adj

[insns-cm_pop]

yes

yes

cm.popret {reg_list}, stack_adj

[insns-cm_popret]

yes

yes

cm.popretz {reg_list}, stack_adj

[insns-cm_popretz]

yes

yes

cm.mva01s rs1', rs2'

[insns-cm_mva01s]

yes

yes

cm.mvsa01 r1s', r2s'

[insns-cm_mvsa01]

1.11. Zcmt

Zcmt adds the table jump instructions and also adds the JVT CSR. The JVT CSR requires a state enable if Smstateen is implemented. See [csrs-jvt] for details.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

Note
 Zcmt is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.

The Zcmt extension depends on the Zca and Zicsr extensions.

RV32 RV64 Mnemonic Instruction

yes

yes

cm.jt index

[insns-cm_jt]

yes

yes

cm.jalt index

[insns-cm_jalt]

1.12. Zc instruction formats

Several instructions in this specification use the following new instruction formats.

Format instructions 15:10 9 8 7 6 5 4 3 2 1 0

CLB

c.lbu

funct6

rs1'

uimm

rd'

op

CSB

c.sb

funct6

rs1'

uimm

rs2'

op

CLH

c.lhu, c.lh

funct6

rs1'

funct1

uimm

rd'

op

CSH

c.sh

funct6

rs1'

funct1

uimm

rs2'

op

CU

c.[sz]ext.*, c.not

funct6

rd'/rs1'

funct5

op

CMMV

cm.mvsa01 cm.mva01s

funct6

r1s'

funct2

r2s'

op

CMJT

cm.jt cm.jalt

funct6

index

op

CMPP

cm.push*, cm.pop*

funct6

funct2

urlist

spimm

op
Note
 c.mul uses the existing CA format