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Simulation of Gray-Code Counter, Ring Counter, and Sequence Generator FSM

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ELL201 Verilog Assignment

Compiling Verilog Code

iverilog -o graycodesim graycode.v tb_graycode.v
iverilog -o ringcountersim ringcounter.v tb_ringcounter.v
iverilog -o sequencesim sequence.v tb_sequence.v

TestBench Results

vvp graycodesim
vvp ringcountersim
vvp sequencesim

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Simulation of Gray-Code Counter, Ring Counter, and Sequence Generator FSM

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