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Data memory waiting #7

Closed

rj45 opened this issue Jun 5, 2021 · 0 comments · Fixed by #20

Owner

rj45 commented Jun 5, 2021

Allow the processor to take multiple cycles to complete a memory read or write, controlled by a busy signal from the memory controller.

Should use a valid/ready handshake. Bonus points if same-cycle access is still supported.

rj45 mentioned this issue

Program memory waiting #8

Open

rj45 mentioned this issue

Multi-cycle microcode and memory access #20

Merged

rj45 closed this as completed in #20

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