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Changed PLL phase shift a little, 24 meg Fast RAM now works for me.
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Alastair M. Robinson committed Oct 9, 2012
1 parent 61d82b5 commit d59ad36
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Showing 6 changed files with 181 additions and 92 deletions.
14 changes: 11 additions & 3 deletions fampiga/board/TG68K.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -177,9 +177,17 @@ BEGIN
ramlds <= lds_in;
ramuds <= uds_in;

ramaddr(23 downto 0) <= cpuaddr(23 downto 0);
ramaddr(24) <= sel_fast;
ramaddr(31 downto 25) <= cpuaddr(31 downto 25);
-- ramaddr(23 downto 0) <= cpuaddr(23 downto 0);
-- ramaddr(24) <= sel_fast;
-- ramaddr(31 downto 25) <= cpuaddr(31 downto 25);

ramaddr(20 downto 0) <= cpuaddr(20 downto 0);
ramaddr(31 downto 24) <= cpuaddr(31 downto 24);
ramaddr(23 downto 21) <= "010" when cpuaddr(23 downto 21)="001" -- 2 -> 4
else "011" when cpuaddr(23 downto 21)="010" -- 4 -> 6
else "100" when cpuaddr(23 downto 21)="011" -- 6 -> 8
else "111" when cpuaddr(23 downto 21)="100" -- 8 -> E
else cpuaddr(23 downto 21); -- pass through others

-- map RAM appropriately:
-- we want 0x200000 to 0x9ffffe to map to
Expand Down
128 changes: 64 additions & 64 deletions fampiga/board/palclk.bsf
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
Expand All @@ -18,95 +18,95 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 256 200)
(rect 0 0 256 184)
(text "palclk" (rect 111 0 151 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 184 25 196)(font "Arial" ))
(text "inst" (rect 8 169 25 180)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
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)
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)
(drawing
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(text "inclk0 frequency: 8.000 MHz" (rect 50 59 170 71)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 73 151 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 75 96 97 108)(font "Arial" ))
(text "Ph (dg)" (rect 105 96 135 108)(font "Arial" ))
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(text "DC (%)" (rect 138 91 306 192)(font "Arial" ))
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(text "c1" (rect 54 117 117 244)(font "Arial" ))
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)
2 changes: 1 addition & 1 deletion fampiga/board/palclk.qip
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.0"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "palclk.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "palclk.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "palclk.ppf"]
46 changes: 23 additions & 23 deletions fampiga/board/palclk.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition
-- 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
-- ************************************************************


--Copyright (C) 1991-2009 Altera Corporation
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
Expand Down Expand Up @@ -138,24 +138,24 @@ ARCHITECTURE SYN OF palclk IS
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
locked : OUT STD_LOGIC
);
END COMPONENT;

BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
locked <= sub_wire5;
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;

Expand All @@ -165,7 +165,7 @@ BEGIN
clk0_divide_by => 11,
clk0_duty_cycle => 50,
clk0_multiply_by => 156,
clk0_phase_shift => "-3105",
clk0_phase_shift => "-2250",
clk1_divide_by => 11,
clk1_duty_cycle => 50,
clk1_multiply_by => 156,
Expand Down Expand Up @@ -232,7 +232,7 @@ BEGIN
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
locked => sub_wire3
);


Expand Down Expand Up @@ -287,7 +287,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "304.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
Expand Down Expand Up @@ -317,12 +317,12 @@ END SYN;
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-126.81818200"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.25000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
Expand Down Expand Up @@ -369,7 +369,7 @@ END SYN;
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "156"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3105"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2250"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "156"
Expand Down Expand Up @@ -439,18 +439,18 @@ END SYN;
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL palclk_wave*.jpg FALSE
Expand Down
3 changes: 2 additions & 1 deletion fampiga/chameleon/fampiga_top.qsf
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Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name VHDL_FILE ../board/chameleon_reconfigure.vhd
set_global_assignment -name VHDL_FILE ../board/chameleon_cdtv_remote.vhd
set_global_assignment -name VHDL_FILE ../board/palclk.vhd
Expand Down Expand Up @@ -205,6 +206,6 @@ set_global_assignment -name VERILOG_FILE ../minimig/PS2Keyboard.v
set_global_assignment -name VERILOG_FILE ../minimig/Sprites.v
set_global_assignment -name VHDL_FILE ../board/chameleon_docking_station.vhd
set_global_assignment -name SDC_FILE fampiga.sdc
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name CDF_FILE Chain1.cdf
set_global_assignment -name QIP_FILE ../board/palclk.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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