Memory forwarding figure, Chisel projects

chisel-book.tex

@@ -1849,11 +1849,22 @@ \section{Memory}
 sometimes can be specified.
 Chisel documents that the read data is undefined.
 
+\begin{figure}
+  \centering
+  \includegraphics[scale=\scale]{figures/memory-forwarding}
+  \caption{A synchronous memory with forwarding for a defined read-during-write behavior.}
+  \label{fig:memory:forwarding}
+\end{figure}
+
 If we want to read out the newly written value, we can build a forwarding
 circuit that detects that the addresses are equal and \emph{forwards} the
-write data.
-Listing~\ref{lst:memory:forward} shows a synchronous memory including
-the forwarding circuit. We need to store the write data into a register
+write data. Figure~\ref{fig:memory:forwarding} shows the memory with
+the forwarding circuit. Read and write addresses are compared and gated with
+write enable to select between the forwarding path of the write data or the
+memory read data. The write data is delayed by one clock cycle with a register.
+
+Listing~\ref{lst:memory:forward} shows the Chisel code for a synchronous memory
+including the forwarding circuit. We need to store the write data into a register
 (\code{wrDataReg}) to be available in the next clock cycle the synchronous
 memory has also a one clock cycle latency.
 We compare the two input addresses (\code{wrAddr} and \code{rdAddr})
@@ -2727,9 +2738,10 @@ \chapter{Design of a Processor}
 
 Leros is designed to be simple, but still a good target for a C compiler.
 The description of the instructions fits on one page, see Table~\ref{tab:leros:isa}.
-In that table A represents the accumulator, PC is the program counter,
-i is an immediate value (0 to 255), Rn a register
-n (0 to 255), o a branch offset relative to PC, and AR an address register for memory access.
+In that table \code{A} represents the accumulator, \code{PC} is the program counter,
+\code{i} is an immediate value (0 to 255), \code{Rn} a register
+\code{n} (0 to 255), \code{o} a branch offset relative to the \code{PC},
+and \code{AR} an address register for memory access.
 
 \begin{table}
 \centering
@@ -2896,7 +2908,7 @@ \section{Assembling Instructions}
 
 \section{Exercise}
 
-This last chapter exercise assignment is in a very free form. You are at the end
+This exercise assignment in one of the last Chapters is in a very free form. You are at the end
 of your learning tour through Chisel and ready to tackle design problems that
 you find interesting.
 
@@ -3113,9 +3125,6 @@ \chapter{Chisel 2}
 \chapter{Summary}
 \label{sec:conclusion}
 
-
-
-
 \section*{Source Access}
 
 This book is available in open source.
@@ -3129,6 +3138,65 @@ \section*{Source Access}
 contains also projects for various popular FPGA boards:
 \url{https://github.com/schoeberl/chisel-examples}
 
+\appendix
+
+\chapter{Chisel Projects}
+
+Chisel is not (yet) used in many projects. Therefore, open-source Chisel code
+to learn the language and the coding style from is rare. Here we list several projects
+we are aware of that use Chisel and are in open source.
+
+\begin{description}
+
+\item[\myref{https://github.com/chipsalliance/rocket-chip}{Rocket}] is an implementation of \myref{https://en.wikipedia.org/wiki/RISC-V}{RISC-V}~\cite{risc-v}, which was
+the first main Chisel project~\cite{rocket:techrep}. Rocket was originally developed at UC
+Berkeley. Rocket is available in open source,
+but also forms the basis for the chip portfolio of \myref{https://www.sifive.com/}{SiFive}.
+The code base at SiFive serves as a major test bench for Chisel and new Chisel features
+need to pass the tests at SiFive.
+% TODO: get an ok from Jack
+
+\item[\myref{https://github.com/ucb-bar/riscv-sodor}{Sodor}] is a collection of RISC-V
+implementations intended for educational use. It contains 1, 2, 3, and 5 stages pipeline
+implementations. All processors use a simple scratchpad memory shared by instruction
+fetch, data access, and program loading via a debug port. Sodor is mainly intended to
+be used in simulation.
+
+\item[\myref{https://github.com/t-crest/patmos}{Patmos}] is an implementation of a
+processor optimized fro real-time systems~\cite{patmos:rts2018}. The Patmos repository
+includes several multicore communication architectures, such as a time-predictable memory
+arbiter~\cite{t-crest:memnoc}, a network-on-chip~\cite{s4nocni:arcs2019}
+a shared scratchpad memory with ownership~\cite{t-crest:ownspm}.
+At the time of this writing, Patmos is still described in Chisel 2.
+
+\item[\myref{https://github.com/pretis/flexpret}{FlexPRET}] is a implementation of a
+precision timed architecture~\cite{Zimmer:EECS-2015-181}. FlexPRET implements
+the RISC-V instruction set and has been updated to Chisel 3.1.
+
+\item[\myref{https://github.com/schoeberl/lipsi}{Lipsi}] is a tiny processor intended
+for utility functions on a system-on-chip~\cite{lipsi:arcs2018}. As the code base of
+Lipsi is very small, it can serve as an easy starting point for processor design in Chisel.
+Lipsi also showcases the productivity of Chisel/Scala. It took me 14 hours to: describe the
+hardware in Chisel and run it on an FPGA, write an assembler in Scala, write a
+Lipsi instruction set simulator in Scala for co-simulation, and write a few test cases
+in Lipsi assembler.
+
+\item[\myref{http://www.opensocfabric.org/}{OpenSoC Fabric}] is an open-source NoC
+generator written in Chisel~~\cite{OpenSoC:ispass2016}. It is intended to provide a
+system-on-chip for large-scale design exploration. The NoC itself is a state-of-the-art design with wormhole routing, credits for flow control, and virtual channels.
+OpenSoC Fabric is still using Chisel~2.
+
+\item[\myref{https://github.com/bu-icsg/xfiles-dana}{RoCC}] is a neural network accelerator
+that integrates with the RISC-V Rocket processor~\cite{RoCC:2015}.
+RoCC supports inference and learning.
+
+\item[ ] 
+\end{description}
+
+If you know an open-source project that uses Chisel, please drop me a note
+so I can include it in a future edition of the book.
+
+
 \chapter{Headings}
 
 \todo{Collect the headings here, but only elevate them to chapter level when some

chisel.bib

@@ -76,3 +76,101 @@ @BOOK{dally:vhdl:2016
   pages = {664}
 }
 
+@techreport{rocket:techrep,
+    Author = {Asanović, Krste and Avizienis, Rimas and Bachrach, Jonathan and Beamer, Scott and Biancolin, David and Celio, Christopher and Cook, Henry and Dabbelt, Daniel and Hauser, John and Izraelevitz, Adam and Karandikar, Sagar and Keller, Ben and Kim, Donggyu and Koenig, John and Lee, Yunsup and Love, Eric and Maas, Martin and Magyar, Albert and Mao, Howard and Moreto, Miquel and Ou, Albert and Patterson, David A. and Richards, Brian and Schmidt, Colin and Twigg, Stephen and Vo, Huy and Waterman, Andrew},
+    Title = {The Rocket Chip Generator},
+    Institution = {EECS Department, University of California, Berkeley},
+    Year = {2016},
+    Month = {Apr},
+    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html},
+    Number = {UCB/EECS-2016-17},
+    Abstract = {Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.}
+}
+
+@INPROCEEDINGS{s4nocni:arcs2019,
+  author = {Martin Schoeberl and Luca Pezzarossa and Jens Spars{\o}},
+  title = {A minimal network interface for a simple network-on-chip},
+  booktitle = {Architecture of Computing Systems - ARCS 2019},
+  year = {2019},
+  editor = {Martin Schoeberl and Thilo Pionteck and Sascha Uhrig and J{\"u}rgen
+	Brehm and Christian Hochberger},
+  pages = {295--307},
+  month = {1},
+  publisher = {Springer},
+  day = {1},
+  doi = {10.1007/978-3-030-18656-2\_22},
+  isbn = {9783030186555},
+  language = {English}
+}
+
+@INPROCEEDINGS{t-crest:memnoc,
+  author = {Martin Schoeberl and David VH Chong and Wolfgang Puffitsch and Jens
+	Spars{\o}},
+  title = {A Time-predictable Memory Network-on-Chip},
+  booktitle = {Proceedings of the 14th International Workshop on Worst-Case Execution
+	Time Analysis (WCET 2014)},
+  year = {2014},
+  pages = {53--62},
+  address = {Madrid, Spain},
+  month = {July},
+  doi = {10.4230/OASIcs.WCET.2014.53},
+  url = {http://www.jopdesign.com/doc/memnoc.pdf}
+}
+
+@INPROCEEDINGS{t-crest:ownspm,
+  author = {Martin Schoeberl and T{\'o}rur Biskopst{\o} Str{\o}m and Oktay Baris
+	and Jens Spars\o{}},
+  title = {Scratchpad Memories with Ownership},
+  booktitle = {2019 Design, Automation and Test in Europe Conference Exhibition
+	(DATE)},
+  year = {2019}
+}
+
+@TECHREPORT{risc-v,
+  author = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanovic,
+        Krste},
+  title = {The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA},
+  institution = {EECS Department, University of California, Berkeley},
+  year = {2011},
+  number = {UCB/EECS-2011-62},
+  month = {May},
+  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.html}
+}
+
+@PHDTHESIS{Zimmer:EECS-2015-181,
+  author = {Zimmer, Michael},
+  title = {Predictable Processors for Mixed-Criticality Systems and Precision-Timed
+        I/O},
+  school = {EECS Department, University of California, Berkeley},
+  year = {2015},
+  month = {Aug},
+  number = {UCB/EECS-2015-181},
+  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.html}
+}
+
+@INPROCEEDINGS{OpenSoC:ispass2016,
+  author = {Farzaf Fatollahi-Fard and David Donofrio and George Michelogiannakis
+	and John Shalf},
+  title = {OpenSoC Fabric: On-chip network generator},
+  booktitle = {2016 IEEE International Symposium on Performance Analysis of Systems
+	and Software (ISPASS)},
+  year = {2016},
+  pages = {194--203},
+  month = {April},
+  doi = {10.1109/ISPASS.2016.7482094}
+}
+
+@INPROCEEDINGS{RoCC:2015,
+author={Schuyler Eldridge and Amos Waterland and Margo Seltzer and Jonathan Appavooand Ajay Joshi},
+booktitle={2015 International Conference on Parallel Architecture and Compilation (PACT)},
+title={Towards General-Purpose Neural Network Computing},
+year={2015},
+volume={},
+number={},
+pages={99--112},
+keywords={feedforward neural nets;learning (artificial intelligence);neural net architecture;recurrent neural nets;general-purpose neural network computing;machine learning;hardware accelerator;software-hardware extension;power consumption;X-FILES;feedforward neural network;feedback neural network;neural network accelerator architecture;DANA;Artificial neural networks;Hardware;Software;Registers;Standards;Accelerator architectures},
+doi={10.1109/PACT.2015.21},
+ISSN={1089-795X},
+month={Oct},}
+
+