bump for chipsalliance/rocket-chip#2841

sequencer · Jan 7, 2022 · cc5db14 · cc5db14
1 parent 9d055fd
commit cc5db14
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -28,6 +28,7 @@ case class MyCoreParams(
   enableToFromHostCaching: Boolean = false,
 ) extends CoreParams {
   val useVM: Boolean = true
+  val useHypervisor: Boolean = false
   val useUser: Boolean = true
   val useSupervisor: Boolean = false
   val useDebug: Boolean = true
@@ -41,6 +42,7 @@ case class MyCoreParams(
   val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
   val nLocalInterrupts: Int = 0
   val useNMI: Boolean = false
+  val nPTECacheEntries: Int = 0 // TODO: Check
   val nPMPs: Int = 0 // TODO: Check
   val pmpGranularity: Int = 4 // copied from Rocket
   val nBreakpoints: Int = 0 // TODO: Check