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[!] rtlgen fix: destructors did not properly generate for the array o…
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…f modules (memory blocks, decoders ,etc)
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sergeykhbr committed Nov 26, 2023
1 parent 8994714 commit 27af9d8
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Showing 20 changed files with 44 additions and 15 deletions.
1 change: 0 additions & 1 deletion sc/rtl/misclib/sfifo.h
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,6 @@ SC_MODULE(sfifo) {
sc_signal<sc_uint<(log2_depth + 1)>> total_cnt;
} v, r;


};

template<int dbits, int log2_depth>
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/cache/lrunway.h
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@ SC_MODULE(lrunway) {
sc_signal<sc_uint<LINE_WIDTH>> mem[LINES_TOTAL];
} v, r;


};

template<int abits, int waybits>
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/cache/pmp.h
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,6 @@ SC_MODULE(PMP) {
PmpTableItemType tbl[CFG_PMP_TBL_SIZE];
} v, r;


};

} // namespace debugger
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10 changes: 10 additions & 0 deletions sc/rtl/riverlib/cache/tagmemcoupled.h
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ SC_MODULE(TagMemCoupled) {

TagMemCoupled(sc_module_name name,
bool async_reset);
virtual ~TagMemCoupled();


private:
Expand Down Expand Up @@ -190,6 +191,15 @@ TagMemCoupled<abus, waybits, ibits, lnbits, flbits>::TagMemCoupled(sc_module_nam
sensitive << i_clk.pos();
}

template<int abus, int waybits, int ibits, int lnbits, int flbits>
TagMemCoupled<abus, waybits, ibits, lnbits, flbits>::~TagMemCoupled() {
for (int i = 0; i < MemTotal; i++) {
if (memx[i]) {
delete memx[i];
}
}
}

template<int abus, int waybits, int ibits, int lnbits, int flbits>
void TagMemCoupled<abus, waybits, ibits, lnbits, flbits>::comb() {
bool v_addr_sel;
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/arith/int_mul.h
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,6 @@ SC_MODULE(IntMul) {
sc_signal<sc_biguint<83>> lvl3[4];
} v, r;


};

} // namespace debugger
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/bp_btb.h
Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,6 @@ SC_MODULE(BpBTB) {

sc_signal<sc_uint<RISCV_ARCH>> dbg_npc[CFG_BP_DEPTH];


};

} // namespace debugger
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/csr.h
Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,6 @@ SC_MODULE(CsrRegs) {
sc_signal<sc_uint<CFG_PMP_FL_TOTAL>> pmp_flags;
} v, r;


};

} // namespace debugger
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13 changes: 13 additions & 0 deletions sc/rtl/riverlib/core/decoder.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -209,6 +209,19 @@ InstrDecoder::InstrDecoder(sc_module_name name,
sensitive << i_clk.pos();
}

InstrDecoder::~InstrDecoder() {
for (int i = 0; i < DEC_NUM; i++) {
if (rv[i]) {
delete rv[i];
}
}
for (int i = 0; i < DEC_NUM; i++) {
if (rvc[i]) {
delete rvc[i];
}
}
}

void InstrDecoder::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
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1 change: 1 addition & 0 deletions sc/rtl/riverlib/core/decoder.h
Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ SC_MODULE(InstrDecoder) {
InstrDecoder(sc_module_name name,
bool async_reset,
bool fpu_ena);
virtual ~InstrDecoder();

void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);

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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/fpu_d/divstage53.h
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@ SC_MODULE(divstage53) {
sc_uint<62> wb_thresh[16];
sc_uint<61> wb_dif[4];


};

} // namespace debugger
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/fpu_d/zeroenc.h
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,6 @@ SC_MODULE(zeroenc) {
private:
sc_signal<sc_uint<shiftwidth>> wb_muxind[(iwidth + 1)];


};

template<int iwidth, int shiftwidth>
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/queue.h
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@ SC_MODULE(Queue) {
sc_signal<sc_biguint<dbits>> mem[DEPTH];
} v, r;


};

template<int abits, int dbits>
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/regibank.h
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,6 @@ SC_MODULE(RegIntBank) {
RegValueType arr[REGS_TOTAL];
} v, r;


};

} // namespace debugger
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/stacktrbuf.h
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,6 @@ SC_MODULE(StackTraceBuffer) {
sc_signal<sc_biguint<(2 * RISCV_ARCH)>> stackbuf[STACK_TRACE_BUF_SIZE];// [pc, npc]
} v, r;


};

} // namespace debugger
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1 change: 0 additions & 1 deletion sc/rtl/riverlib/core/tracer.h
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,6 @@ SC_MODULE(Tracer) {
std::string tracestr;
FILE *fl;


};

} // namespace debugger
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10 changes: 10 additions & 0 deletions sc/rtl/techmap/mem/ram_bytes_tech.h
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ SC_MODULE(ram_bytes_tech) {
SC_HAS_PROCESS(ram_bytes_tech);

ram_bytes_tech(sc_module_name name);
virtual ~ram_bytes_tech();


private:
Expand Down Expand Up @@ -97,6 +98,15 @@ ram_bytes_tech<abits, log2_dbytes>::ram_bytes_tech(sc_module_name name)
}
}

template<int abits, int log2_dbytes>
ram_bytes_tech<abits, log2_dbytes>::~ram_bytes_tech() {
for (int i = 0; i < dbytes; i++) {
if (mem[i]) {
delete mem[i];
}
}
}

template<int abits, int log2_dbytes>
void ram_bytes_tech<abits, log2_dbytes>::comb() {
sc_uint<dbits> vb_rdata;
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10 changes: 10 additions & 0 deletions sc/rtl/techmap/mem/ram_cache_bwe_tech.h
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ SC_MODULE(ram_cache_bwe_tech) {
SC_HAS_PROCESS(ram_cache_bwe_tech);

ram_cache_bwe_tech(sc_module_name name);
virtual ~ram_cache_bwe_tech();


private:
Expand Down Expand Up @@ -89,6 +90,15 @@ ram_cache_bwe_tech<abits, dbits>::ram_cache_bwe_tech(sc_module_name name)
}
}

template<int abits, int dbits>
ram_cache_bwe_tech<abits, dbits>::~ram_cache_bwe_tech() {
for (int i = 0; i < (dbits / 8); i++) {
if (rx[i]) {
delete rx[i];
}
}
}

template<int abits, int dbits>
void ram_cache_bwe_tech<abits, dbits>::comb() {
sc_biguint<dbits> vb_rdata;
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1 change: 0 additions & 1 deletion sc/rtl/techmap/mem/ram_mmu_tech.h
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,6 @@ SC_MODULE(ram_mmu_tech) {
sc_biguint<dbits> rdata;
sc_biguint<dbits> mem[DEPTH];


};

template<int abits, int dbits>
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1 change: 0 additions & 1 deletion sc/rtl/techmap/mem/ram_tech.h
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,6 @@ SC_MODULE(ram_tech) {
sc_uint<dbits> rdata;
sc_uint<dbits> mem[DEPTH];


};

template<int abits, int dbits>
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1 change: 0 additions & 1 deletion sc/rtl/techmap/mem/rom_inferred_2x32.h
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,6 @@ SC_MODULE(rom_inferred_2x32) {
sc_uint<32> mem0[DEPTH];
sc_uint<32> mem1[DEPTH];


};

template<int abits>
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