DAC Digital Trace Termiantion Improvements #63
Comments
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Did you check operation without termination? Did U observe the clock edges with low capacitance probe? |
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I've checked the DAC operates fine without termination on channels 4 and 27 (longest digital trace). Here is a comparrison of the clock line with and without termination. I measured this using a 9.5 pF, 500 MHz, 10:1 passive probe and a high impedance scope.
The markers represent the logic thresholds of 10%/90% of 3.3 V. These both look acceptable to me. Edit: fix images and soldered on better ground connection. |
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@pathfinder49 BTW that scope has a web interface that lets you get screen grabs directly without having to use your camera phone. Can you set cursors on the logic thresholds specified in the DAC data sheet please? |
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Updated my post as requested |
There are 2 different statements in the data-sheet on logic levels.
The schematics show VLOGIC & VDD connected to the P5V4 plane. Measuring on the board confirms VLOGIC & VDD being P5V4. Am I missing something or are the Fastino DACs being driven outside spec? |
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They also spec hold timings for low 0V/high 3V in the table, so presumably that's also valid. (The hold time is a bit longer for that, which makes sense.) |
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(Requiring anything but "comfortably" below 0.8V/above 2.4V with some allowance for PVT changes would be very unusual for these kinds of slow-ish serial interfaces. While issues like this in the analog part would definitely be worth worrying about, I'd not expect any problems from the digital logic here unless we are using super-aggressive timings.) |
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@pathfinder49 There is nothing wrong with the logic levels. The page 4 states the requirements while the page 4 defines the measurement conditions. |
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It looks like the ICE40 has high-enough output impedance. It is not specified in the datasheet. I extrapolated it to be something like 20Ohm, but it looks like it was higher and indeed, it is sufficient as a series termination. 9pf of scope capacitance is quite a lot. I have sub-pf probes but don't have any Fastino to look at it. 9pF of capacitance gives Z=117Ohm at 3-rd harmonic, so these plots are not representative. On the other side, the ADC has 10pf capacitance... |
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@pathfinder49 which probe are you using? The 500MHz 10:1 passive probes that go with the MSO should be much less than that. |
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Also remember to be careful to minimise ground inductance here—don’t use a croc clip, use a sprig clip to ground to somewhere a mm or two from the probe tip |
Nope, those are ~10 pF, like most 10:1 probes (and, to come to Marius's defense here, I don't think we have any nice active probes). |
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Ok! I stand corrected, I thought it was lower. The other option is to fall back to soldering a 500R SMT onto the pad as a probe tip and then solder the end to some coax with the shield pig tailed and soldered to the ground plane. But we should but a fet probe... |
I soldered a pin onto the CMC ground pad of ch27 and clipped the scope ground onto that. |
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The easiest low capacitance 1:10 probe is 450R resistor (2x 910R 0603) in series with a piece of 50Ohm coax cable. Such a probe gives very low rise time and keeps the same 500R impedance up to the GHz range. |
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@gkasprow you reccomended series termination. What resisor valus would you use? I've estimated the trace impedance as ~50 Ohm. However, I'm struggling to find values for the FPGA output imedance. Also, CLRn is a multi-drop bus. Do you believe series terminating this at the FPGA will be adequate? Edit: From my reading it seems like star routing the CLRn is the only reasonable alternative. |
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I've now got a 1 pF, 1 GHz probe. There is a clear difference between terminated and un-terminated performance. (Scope traces are with persistence enabled.)
Though the un-terminated SCLK trace oscillates, it has a slightly bigger signal to logic threshold margin. |
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Nice! If that’s the worse channel I don’t see any evidence of a si issue there (not near a double triggering) @gkasprow the overshoot is ~1V do you think that will lead to worse digital feed through (eg when the diodes conduct?) I guess the answer to my question is “no” since @pathfinder49 has measured the noise and checked that it gets better not worse when we dnp the termination. Based on these measurements does everyone agree we should dnp the shunt terminations but consider adding a small (10R?) series termination at the FPGA? |
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Be careful with 1V overshoots because they can open the protection diodes and cause current peaks that may interfere with circuits that were not designed to act like the clamping circuits. For example, old PCI used such an approach. The best series termination is probably something between 10 and 20 Ohm. |
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@gkasprow why do you think the transients aren't clipped to -0.3V by the diodes? I don't see any evidence of clipping in the data that @pathfinder49 posted. Do you think it's a measurement artifact (e.g. ringing in the probe due to ground inductance?) |
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NB Vdd is 5V4 for the DAC, so only the negative transients could prove problematic. In any case, it sounds like a good plan for the next revision is:
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Overshoot or undershoot that are outside the spec are a massive problem. We can't sell or support systems that knowingly and intentionally exceed specs for no good reason. Whether there is added noise or activated clamping diodes or not doesn't matter. |
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To state that "the termination is not required" is also speculative and potentially very wrong, since for example there hasn't been any analysis of the effect of unterminated bounce on the FPGA. |
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@jordens sure. The plan is to add source termination in the next revision and take more measurements before making any decisions. I'm happy to keep the default population option being AC shunt terminations populated and series terminations 0R for the next revision to minimize the chances of breakage.
The point I was making to Greg wasn't that we shouldn't ignore the bounce, but rather that the lack of clamping could be indicative of a measurement error (in which case we might want to take a bit more data before making any decisions). I don't have well-calibrated intuitions here so am discussing what to do with @gkasprow |
AFAICS clamping is consistent with what you measure. Given the ringing period, probe impedance and bandwidth I would not expect a clamped waveform to look much different. |
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One other thought here... The aim of the shunt termination is to suppress ringing at frequencies where the wavelength becomes comparable to the trace length. However, our main concern for digital-analog cross-talk is frequencies close to the filter cut-off; high frequency components can easily be filtered out later if the application is sensitive to them. This From the data @pathfinder49 posted, the ringing period looks to be approx 4ns, so 250MHz. However, the pole in the current termination is 16MHz. @pathfinder49 can you see what the ringing looks like with a 10pF termination capacitor? That should buy 20dB on the spurs due to the termination. It may be possible to reduce the capacitor further/eliminate it once we add series termination, but we'll want to measure that. |
What's your model for this? I think it's quite likely that the termination related crosstalk couples into other channels after the filter. |
Answering my own question, I don't think it is a measurement artifact because of the data that @pathfinder49 posted with the shunt termination, showing no significant ringing.
Te probe 3dB bandwidth is 1.5GHz, which is quite a bit higher than the ringing frequency. The impedance is 1pF which is relatively small compared with other capacitances around. Anyway, I would have expected clipping to have introduced some asymmetry since clipping only occurs on the low logic level not the higher one. |
pathfinder49
changed the title
Here is the SCLK line of ch27 at the FPGA when operating without termination. This is within the FPGA spec. Series-termination should therefore work fine. |
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We have two options for reducing crosstalk from the termination:
Option 2. seems like the better solution. Unless there are objections, I will switch to series termination. |
Dead-bugged, or just soldered them onto the pads? |
What's the undershoot (min negative value measured) with the 10pF capacitors? For the next revision we should aim to keep the worst-case undershoot to ~200mV to give us some margin. I'd guess that will be something in the 10-20pF range. Once we have the new hw with pads for series termination we can quickly have a play and find something closer to optimal... |
Do we win anything by removing the pads for the shunt terminations? If it's not a problem for the layout, I'd prefer to have the option for both shunt and series termination in the next revision. Maybe go for 20pF shunt and 0R series. Then order some hw to play with, with the aim of optimizing values for the v1.3 hw. IIUC, in the current hardware it's hard to know how much impact the shunt termination has on the noise since the "spur floor" is set by the vias/routing. Once we fix this we should be able to get better data and make an informed decision. |
Space, though not a major concern. The current 0201 capacior size is not very convenient for reworking the board. With 0603 caps, the termination becomes much larger.
Why not use series termination by default? As I understand it, the only downside of this is that it does not give a nice waveform at the FPGA. However, the reflections to the FPGA are within the FPGA spec.
This is not correct. The current termination causes crosstalk-spurs of ~-70 dBmV. |
Well, if we have space to spare then it's not a concern. If we're pushed then we should consider this more seriously.
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Because what we have currently works pretty well. The series termination should work fine, but will need testing. If we leave both options open then we know that after a quick bit of testing we'll be able to find something that works nicely. We may also find that a combination of series and shunt termination provides the best overall solution.
Ok. Thanks for the reminder. How much lower was it without termination? |
If there is no other significant coupling-mechanism, the spurs became undetectable (measurement noise floor -85 dBmV) |
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So we have no evidence for termination making more than a factor of ~4 difference to the spur. That suggests that reducing the capacitor to 20pF should reduce the spur to our noise floor while still providing an excellent termination. If the series termination works well we can completely remove the shunt termination in a future revision but let’s keep it for now unless we find a good reason to remove it. |
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Put it another way: don’t underestimate how much of your life it will take to add and route all those series terminations and then test to make sure all works. If you can get the same effect by just changing cap values then surely that’s what we should do... |
I've updated my post with a clearer 10 pF trace and a 15pF trace. Measuring forr a minute, 10pF gives a minimum of -0.295 V. This is within the DAC spec. |
Sounds good. Let's go for 15pF. |
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I've tired different series terminations by cutting the ch31 SCLK trace close to the FPGA. I then bridged the gap with different resistors. Parallel termination has been removed. Waveforms were measured at the ch31 SCLK test-point. This is adjacent to the DAC. Series termination works well. From my measurements, I'd choose a series resistance of ~80 Ohm.
Based on these results, I will use 80 ohm series termination and DNP the parallel termination. |
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Nice job @pathfinder49 ! The other thing one needs to be aware of with series termination is the signal rise time, since you're now creating an RC filter with the trace capacitance. I don't see a specification for that in the data sheet, but the 51Ohm trace you post certainly looks fine to me. What was the undershoot in that case? @gkasprow what do you think? This seems somewhat higher than the series termination values you expected from your calculation... Anyway, DNPing the shunt termination pads and adding a ~50Ohm series termination seems like a relatively safe bet for the next revision. We should consider only stuffing one board initially and double checking the SI before stuffing the rest. |
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making 80Ohm traces can be hard for existing stack up. |
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@gkasprow Indeed, this is likely more RC filtering than termination. I suspect it will have a pretty similar effect to just decreasing the FPGA drive strength (although, IIRC we can't do that on these FPGAs, can we?). Am I right that from the numbers you posted above, the transmission line is decently source terminated by the FPGA? But, if you're happy with the rise-time for those traces, is there any reason that the series resistor wouldn't be an acceptable solution to the problem? |
about 150 mV. From my measurements, resistors smaller than ~70 ohm have some overshoot. Resistors larger than ~80 ohm get a 2 step rising/falling edge.
I'm inclined to err on the side of a higher resistance as:
I'm using 82 ohm, 0201 resistors for the series termination (space constraints close to the FPGA). I will keep parallel termination, but not populate the 0603 capacitors. This should allow fairly easy switching to parallel termination if required. |
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sounds like a good plan |
You haven't demonstrated that AFAICT. That would require a simultaneous measurement of both the clock and data lines. Trigger the measurement from the clock and look at the "eye" for the data. Looking at the clock doesn't tell you everything. e.g. about skew between the data and clock lines, or any timing jitter between the two. |
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Also, there are generally requirements for minimum edge rate at the transition. Slow edges can cause issues with the sampling logic. This DAC doesn't specify the max signal rise time, but it is likely still sensitive to it (any ideas @gkasprow about what we should aim for?). Anyway, I'm fine with sticking the pads in for the series resistor (since you're using a combined resistance, including the FPGA drivers, that's larger than the trace impedance, it's not really matching as much as filtering). DNP the shunt termination and take more data once the next hw revision arrives. NB since the trace capacitance varies significantly between channels, we'll need to re-check on more channels on the new hw. |
Footnote 2 on page 6 of the data sheet states:
This isn't a maximum, but our rise times are well within spec. |
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Ok. Good for you for digging out the data! So we should aim to keep the 90/10 rise/fall time below 3ns. It's hard to tell accurately by eye but for the 80Ohm resistor it doesn't look like we're so much better than that. For the 50Ohm one we have a decent amount of margin. I'd be more inclined to go for a 50R resistor since it feels like the margin is quite comfortable in both rise time and ringing. Before we do that, we should check that the FPGA doesn't have a variable drive strength that would achieve the same result. Do you know @jordens / @gkasprow ? |
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Only the High Current IOs have configurable strength. They do not exist in the particular chip we use. |
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Cool let’s go for the resistors then. Good work on the systematic investigation @pathfinder49 ! |
The termination degrades Fastino performance and is not needed. See below:
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