Skip to content

Home

Jump to bottom
Marius Weber edited this page Feb 13, 2021 · 18 revisions

Fastino

Fast 32-channel, 3MS/s per channel, 16bit DAC EEM card compatible with Zotino.

Design files (schematics, PCB layouts, BOMs) can be found at Fastino/Releases.

Gateware development at QUARTIQ/fastino

Specs

  • 32 channels, 2 M/s simultaneous, 16 bit: 1 Gb/s aggregate
  • AFE/DAC: from Stabilizer, maybe modified, similar bandwidth, range
  • Interface: single EEM (more EEM if there are pins and space)
  • Data/clock/LDAC masking on channels for intervals to suppress digital feedthrough
  • LEDs
  • No contention between configuration and data
  • Update rate on DAC masking: ~1 µs

Components

  • HW specification/review/codesign/input
  • Phy layer of framed data at 1 Gb/s over multilane LVDS with slower return channel (1 EEM), serialization/deserialzation/framing
    • this sounds very much like channel link/camera link, TI serdes chips.
  • DAC interface: PLL for SPI bitclock, sample clocking, CLR, LDAC
  • Out-of-band configuration layer: configuration, LEDs, clocking, channel masking
  • RTIO channel design
    • baseline: 32x16 bit=512 bit DAC data events on existing kernel/DMA/DRTIO infrastructure
    • later: optimize DMA/Fastino-DMA/DRTIO/DDMA to achieve 2 M/s 512 b events
  • ARTIQ coredevice API
  • docs, examples, tests
  • CI
  • Option: Interpolator to 2 MS/s @ 32 channels

API

  • identify
  • set LEDs
  • TBD: tune clock skew?
  • set masked channels
  • submit DAC data (all channels)
  • later option: interpolation ratio
  • later option: 2D arrays of a configurable subset of channels at given sample rate
  • later option: per-channel sine generation (e.g. for tickling)
  • later option: per-channel offsets in gateware (e.g. compensate stray fields without re-uploading shuttling waveforms) or composing waveforms
  • later option: per-channel clipping/limiting in gateware
  • later option: dynamic/configurable sample clock alignment to below the DAC granularity, i.e. variable sample phase

Noise Performance

When suitably configured, Fastino has spur-free output signals in the 100 kHz to 5 MHz frequency range. Noise characterisation mesurements with and without DAC updates can be found in the issue discussions.

  • Suitable configurations for low noise performance are explored in #56. Though measured with Fastino v1.0, the measured noise characteristics are still applicable. The measurements also demonstrate how to reduce all noise-spurs in the 100 kHz to 5 MHz range (no digital updates).
  • Digital updates cause measurable spurs in the Fastino analogue outputs. Fastino revisions v1.1 and v1.2 reduce the this digital to analogue crosstalk. Some measurements for Fastino revisions v1.0, v1.1 and v1.2 are found in #62, #75 and #85 respectively.

Roadmap

  • Prototype serializer/deserializer on Kasli+Banker/Humpback
  • Measure RTIO/DMA/DRTIO throughput at 512b events
  • Hardware
  • DAC interface
  • RTIO components
  • Masking/configuration/version/identification channel
  • coredevice API

Link prototype

https://github.com/quartiq/fastino

Fastino

Main Sinara Wiki

Clone this wiki locally