Updated Reset counter process

added dcm_locked to sensitivity list
ska-sa · Jan 17, 2018 · 84aa4be · 84aa4be
1 parent efe9ca2
commit 84aa4be
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/jasper_library/hdl_sources/forty_gbe/forty_gbe.vhd b/jasper_library/hdl_sources/forty_gbe/forty_gbe.vhd
@@ -1375,7 +1375,7 @@ begin
 
     -- GT 29/03/2017 NEED TO ENSURE FIRMWARE IS RESET AS FPGA BOOTS
     -- FROM SDRAM RECONFIGURATION, WAS ONLY BEING RESET ON POWER UP
-    gen_fpga_reset_counter : process(FPGA_RESET_N, sys_clk)
+    gen_fpga_reset_counter : process(FPGA_RESET_N, dcm_locked, sys_clk)
       begin
           if (FPGA_RESET_N = '0' or dcm_locked = '0')then
               fpga_reset_counter <= (others => '0');