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bus_dual_port_ram mods
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library block and fix to we proms
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@amartens
amartens committed Dec 15, 2017
1 parent 35d4c04 commit bef2117
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Showing 2 changed files with 6 additions and 67 deletions.
8 changes: 4 additions & 4 deletions casper_library/bus_dual_port_ram_init.m
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Expand Up @@ -397,8 +397,8 @@ function bus_dual_port_ram_init(blk, varargin)
if (banks > 1),
ypos_tmp = ypos_tmp + bus_expand_d*replication/2;
reuse_block(blk, 'prom_wea', 'xbsIndex_r4/ROM', ...
'depth', num2str(banks), 'latency', '0', 'distributed_mem', 'Distributed memory', ...
'initVector', mat2str([zeros(1, banks/2), 2.^[0:(banks/2)-1]]), ...
'depth', num2str(banks*2), 'latency', '0', 'distributed_mem', 'Distributed memory', ...
'initVector', mat2str([zeros(1, banks), 2.^[banks-1:-1:0]]), ...
'arith_type', 'Unsigned', 'n_bits', num2str(banks), 'bin_pt', '0', ...
'Position', [xpos-prom_w/2 ypos_tmp-prom_d/2 xpos+prom_w/2 ypos_tmp+prom_d/2]);
add_line(blk, 'concata/1', 'prom_wea/1');
Expand All @@ -408,8 +408,8 @@ function bus_dual_port_ram_init(blk, varargin)
ypos_tmp = ypos_tmp + yinc + bus_expand_d*ctiv; %dinb
ypos_tmp = ypos_tmp + bus_expand_d*replication/2;
reuse_block(blk, 'prom_web', 'xbsIndex_r4/ROM', ...
'depth', num2str(banks), 'latency', '0', 'distributed_mem', 'Distributed memory', ...
'initVector', mat2str([zeros(1, banks/2), 2.^[0:(banks/2)-1]]), ...
'depth', num2str(banks*2), 'latency', '0', 'distributed_mem', 'Distributed memory', ...
'initVector', mat2str([zeros(1, banks), 2.^[banks-1:-1:0]]), ...
'arith_type', 'Unsigned', 'n_bits', num2str(banks), 'bin_pt', '0', ...
'Position', [xpos-prom_w/2 ypos_tmp-prom_d/2 xpos+prom_w/2 ypos_tmp+prom_d/2]);
add_line(blk, 'concatb/1', 'prom_web/1');
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65 changes: 2 additions & 63 deletions casper_library/casper_library_bus_init.m
View file
Expand Up @@ -239,37 +239,9 @@ function casper_library_bus_init()
'Position', sprintf('[120 372 195 448]'), ...
'Tag', sprintf(''));

add_block('built-in/SubSystem', [blk,'/bus_dual_port_ram']);
bus_dual_port_ram_gen([blk,'/bus_dual_port_ram']);
add_block('casper_library_bus/bus_dual_port_ram', [blk,'/bus_dual_port_ram']);
set_param([blk,'/bus_dual_port_ram'], ...
'n_bits', sprintf('0'), ...
'bin_pts', sprintf('17'), ...
'init_vector', sprintf('[[-2:1/(2^10):2-(1/(2^10))]'']'), ...
'max_fanout', sprintf('4'), ...
'mem_type', sprintf('Block RAM'), ...
'bram_optimization', sprintf('Area'), ...
'async_a', sprintf('off'), ...
'async_b', sprintf('off'), ...
'misc', sprintf('off'), ...
'bram_latency', sprintf('2'), ...
'fan_latency', sprintf('1'), ...
'addra_register', sprintf('off'), ...
'addra_implementation', sprintf('core'), ...
'dina_register', sprintf('off'), ...
'dina_implementation', sprintf('core'), ...
'wea_register', sprintf('off'), ...
'wea_implementation', sprintf('core'), ...
'ena_register', sprintf('off'), ...
'ena_implementation', sprintf('core'), ...
'addrb_register', sprintf('off'), ...
'addrb_implementation', sprintf('core'), ...
'dinb_register', sprintf('off'), ...
'dinb_implementation', sprintf('core'), ...
'web_register', sprintf('off'), ...
'web_implementation', sprintf('core'), ...
'enb_register', sprintf('off'), ...
'enb_implementation', sprintf('core'), ...
'Position', sprintf('[320 254 395 330]'), ...
'Position', sprintf('[320 251 395 329]'), ...
'Tag', sprintf(''));

add_block('built-in/SubSystem', [blk,'/bus_delay']);
Expand Down Expand Up @@ -746,39 +718,6 @@ function bus_maddsub_init(blk)

end % bus_maddsub_init

function bus_dual_port_ram_gen(blk)

bus_dual_port_ram_mask(blk);
bus_dual_port_ram_init(blk);
set_param(blk, ...
'MaskInitialization', sprintf('bus_dual_port_ram_init(gcb, ...\n ''n_bits'', n_bits, ...\n ''bin_pts'', bin_pts, ...\n ''init_vector'', init_vector, ...\n ''max_fanout'', max_fanout, ...\n ''mem_type'', mem_type, ...\n ''bram_optimization'', bram_optimization, ...\n ''async_a'', async_a, ...\n ''async_b'', async_b, ...\n ''misc'', misc, ...\n ''bram_latency'', bram_latency, ...\n ''fan_latency'', fan_latency, ...\n ''addra_register'', addra_register, ...\n ''addra_implementation'', addra_implementation, ...\n ''dina_register'', dina_register, ...\n ''dina_implementation'', dina_implementation, ...\n ''wea_register'', wea_register, ...\n ''wea_implementation'', wea_implementation, ...\n ''ena_register'', ena_register, ...\n ''ena_implementation'', ena_implementation, ...\n ''addrb_register'', addrb_register, ...\n ''addrb_implementation'', addrb_implementation, ...\n ''dinb_register'', dinb_register, ...\n ''dinb_implementation'', dinb_implementation, ...\n ''web_register'', web_register, ...\n ''web_implementation'', web_implementation, ...\n ''enb_register'', enb_register, ...\n ''enb_implementation'', enb_implementation);'));

end % bus_dual_port_ram_gen

function bus_dual_port_ram_mask(blk)

set_param(blk, ...
'Mask', sprintf('on'), ...
'MaskSelfModifiable', sprintf('on'), ...
'MaskType', sprintf('bus_dual_port_ram'), ...
'MaskDescription', sprintf('RAM for a bus allowing fanout control'), ...
'MaskPromptString', sprintf('data word bit widths|data word binary points|initial value vector|limit fanout to ?|memory type|memory optimization|a asynchronous |b asynchronous|misc support|bram latency|input register latency|addra input register|addra register implementation|dina input register|dina register implementation|wea input register|wea register implementation|ena input register|ena register implementation|addrb input register|addrb register implementation|dinb input register|dinb register implementation|web input register|web register implementation|enb input register|enb register implementation'), ...
'MaskStyleString', sprintf('edit,edit,edit,edit,popup(Distributed memory|Block RAM),popup(Area|Speed),checkbox,checkbox,checkbox,edit,edit,checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral)'), ...
'MaskTabNameString', sprintf('basic,basic,basic,basic,basic,basic,basic,basic,basic,latency,latency,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation'), ...
'MaskCallbackString', sprintf('||||||||||||||||||||||||||'), ...
'MaskEnableString', sprintf('on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on'), ...
'MaskVisibilityString', sprintf('on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on'), ...
'MaskToolTipString', sprintf('on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on'), ...
'MaskVariables', sprintf('n_bits=@1;bin_pts=@2;init_vector=@3;max_fanout=@4;mem_type=&5;bram_optimization=&6;async_a=&7;async_b=&8;misc=&9;bram_latency=@10;fan_latency=@11;addra_register=&12;addra_implementation=&13;dina_register=&14;dina_implementation=&15;wea_register=&16;wea_implementation=&17;ena_register=&18;ena_implementation=&19;addrb_register=&20;addrb_implementation=&21;dinb_register=&22;dinb_implementation=&23;web_register=&24;web_implementation=&25;enb_register=&26;enb_implementation=&27;'), ...
'MaskValueString', sprintf('0|17|[[-2:1/(2^10):2-(1/(2^10))]'']|4|Block RAM|Area|off|off|off|2|1|off|core|off|core|off|core|off|core|off|core|off|core|off|core|off|core'), ...
'BackgroundColor', sprintf('[0.501961, 1.000000, 0.501961]'));

end % bus_dual_port_ram_mask

function bus_dual_port_ram_init(blk)

end % bus_dual_port_ram_init

function bus_delay_gen(blk)

bus_delay_mask(blk);
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