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Has the IP core changed in newer Xilinx versions?
The text was updated successfully, but these errors were encountered:
Merge pull request #12 from ianmalcolm/jasper_devel
d45775a
Remove start_done and start_reg from i2c_master_byte_ctrl.v
wnew
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Has the IP core changed in newer Xilinx versions?
The text was updated successfully, but these errors were encountered: