Transfer data double times

[snowprogrammer]

Hello. I use litex to build a SoC with this CPU and wishbone as bus. In my structure, ROM transfers instruction to CPU 2 times (in 2 periods) and the second one is fetched in CPU. Is there a way to change the transfer model for each data one time?

Here is my waveform:

[Dolu1990]

Hi,

Not with the wishbone bus, main issue is that memory need 1 cycle latency at least, but wishbone in its vanilla variant can't map that without tricky tricks.
So, not possible.