About the Csr registers in Vexriscv

[ic-hjx]

Hello! I've encountered some issues while trying to read the mcycle register of VexRiscv. I attempted to add the following function to my C program:

uint64_t read_cycle(void) {
    uint32_t low, high;
    __asm__ ("csrr %0, %1" : "=r" (low), "=r" (high) : "a" (0xc00)); // CSRR instruction to read the cycle register
    return ((uint64_t)high << 32) | low;
}

However, the program compilation returned the following error:

src/main.c: In function 'read_cycle':
src/main.c:145:5: error: impossible constraint in 'asm'
  145 |     __asm__ ("csrr %0, %1" : "=r" (low), "=r" (high) : "a" (0xc00)); 
      |     ^~~~~~~

I'm not sure if there's a syntax issue with my code, and I'm also uncertain about the register number for mcycle in VexRiscv. The information I obtained from the source code seems to indicate 0xc00. Additionally, I'm using the briey-soc architecture, and I noticed that the read access permission for mcycleAccess was not enabled when using CsrPlugin in briey. Therefore, I modified one setting as follows:

new CsrPlugin(
    config = CsrPluginConfig(
        catchIllegalAccess = false,
        mvendorid      = null,
        marchid        = null,
        mimpid         = null,
        mhartid        = null,
        misaExtensionsInit = 66,
        misaAccess     = CsrAccess.NONE,
        mtvecAccess    = CsrAccess.NONE,
        mtvecInit      = 0x80000020l,
        mepcAccess     = CsrAccess.READ_WRITE,
        mscratchGen    = false,
        mcauseAccess   = CsrAccess.READ_ONLY,
        mbadaddrAccess = CsrAccess.READ_ONLY,
        mcycleAccess   = CsrAccess.READ_ONLY, // origin: CsrAccess.NONE
        minstretAccess = CsrAccess.NONE,
        ecallGen       = false,
        wfiGenAsWait         = false,
        ucycleAccess   = CsrAccess.NONE,
        uinstretAccess = CsrAccess.NONE
    )
)

Additionally, I've noticed that the mtime register seems to be unimplemented in VexRiscv?
I am looking forward to and greatly appreciate your response！

[Dolu1990]

Hi, your issue is purly software for now. This isn't realted to VexRiscv
Personnaly i'm using that to read CSR :
https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/riscv.h#L89

[ic-hjx]

I am sorry for that I have open the issue in a wrong place. My questions about the Csr registers in VexRISCV mainly pertain to the identification numbers corresponding to different registers, in the program description that I can found in riscv.h :

#define RDCYCLE 0xC00 //Read-only cycle Cycle counter for RDCYCLE instruction.
#define RDTIME 0xC01 //Read-only time Timer for RDTIME instruction.
#define RDINSTRET 0xC02 //Read-only instret Instructions-retired counter for RDINSTRET instruction.
#define RDCYCLEH 0xC80 //Read-only cycleh Upper 32 bits of cycle, RV32I only.
#define RDTIMEH 0xC81 //Read-only timeh Upper 32 bits of time, RV32I only.
#define RDINSTRETH 0xC82 //Read-only instreth Upper 32 bits of instret, RV32I only.

Now I understand that VexRISCV supports the standard Csr register configuration, which has resolved my issue. Thank you very much!