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compress/qat: enable compression on GEN3
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[ upstream commit da573c0 ]

This patch enables the compression on QAT GEN3 (on hardware
versions that support it) and changes the error message shown
on older hardware versions that don't support the compression.

It also fixes the crash that happened on IM buffer allocation
failure (not enough memory) during the PMD cleaning phase.

Fixes: a124830 ("compress/qat: enable dynamic huffman encoding")
Fixes: 3523327 ("compress/qat: add dynamic SGL allocation")

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
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@steevenlee
Adam Dybkowski authored and steevenlee committed Jun 8, 2021
1 parent 95fd32f commit afe3a7f
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Showing 2 changed files with 79 additions and 39 deletions.
7 changes: 4 additions & 3 deletions drivers/compress/qat/qat_comp.c
View file
Expand Up @@ -191,8 +191,8 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,
ICP_QAT_FW_COMP_EOP
: ICP_QAT_FW_COMP_NOT_EOP,
ICP_QAT_FW_COMP_NOT_BFINAL,
ICP_QAT_FW_COMP_NO_CNV,
ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
ICP_QAT_FW_COMP_CNV,
ICP_QAT_FW_COMP_CNV_RECOVERY);
}

/* common for sgl and flat buffers */
Expand Down Expand Up @@ -603,7 +603,8 @@ qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie,
rx_op->status = RTE_COMP_OP_STATUS_ERROR;
rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
*op = (void *)rx_op;
QAT_DP_LOG(ERR, "QAT has wrong firmware");
QAT_DP_LOG(ERR,
"This QAT hardware doesn't support compression operation");
++(*dequeue_err_count);
return 1;
}
Expand Down
111 changes: 75 additions & 36 deletions drivers/compress/qat/qat_comp_pmd.c
View file
Expand Up @@ -82,13 +82,13 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
= NULL;

for (i = 0; i < qp->nb_descriptors; i++) {

struct qat_comp_op_cookie *cookie = qp->op_cookies[i];
if (qp != NULL)
for (i = 0; i < qp->nb_descriptors; i++) {
struct qat_comp_op_cookie *cookie = qp->op_cookies[i];

rte_free(cookie->qat_sgl_src_d);
rte_free(cookie->qat_sgl_dst_d);
}
rte_free(cookie->qat_sgl_src_d);
rte_free(cookie->qat_sgl_dst_d);
}

return qat_qp_release((struct qat_qp **)
&(dev->data->queue_pairs[queue_pair_id]));
Expand Down Expand Up @@ -198,7 +198,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
struct array_of_ptrs *array_of_pointers;
int size_of_ptr_array;
uint32_t full_size;
uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
uint32_t offset_of_flat_buffs;
int i;
int num_im_sgls = qat_gen_config[
comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
Expand All @@ -213,31 +213,31 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
return memzone;
}

/* Create a memzone to hold intermediate buffers and associated
* meta-data needed by the firmware. The memzone contains 3 parts:
/* Create multiple memzones to hold intermediate buffers and associated
* meta-data needed by the firmware.
* The first memzone contains:
* - a list of num_im_sgls physical pointers to sgls
* - the num_im_sgl sgl structures, each pointing to
* QAT_NUM_BUFS_IN_IM_SGL flat buffers
* - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL
* buffers, each of buff_size
* All other memzones contain:
* - the sgl structure, pointing to QAT_NUM_BUFS_IN_IM_SGL flat buffers
* - the flat buffers: QAT_NUM_BUFS_IN_IM_SGL buffers,
* each of buff_size
* num_im_sgls depends on the hardware generation of the device
* buff_size comes from the user via the config file
*/

size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
& QAT_64_BYTE_ALIGN_MASK;
offset_of_flat_buffs =
offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
offset_of_flat_buffs = sizeof(struct qat_inter_sgl);
full_size = offset_of_flat_buffs +
num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
buff_size * QAT_NUM_BUFS_IN_IM_SGL;

memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
memzone = rte_memzone_reserve_aligned(inter_buff_mz_name,
size_of_ptr_array,
comp_dev->compressdev->data->socket_id,
RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN);
if (memzone == NULL) {
QAT_LOG(ERR, "Can't allocate intermediate buffers"
" for device %s", comp_dev->qat_dev->name);
QAT_LOG(ERR,
"Can't allocate intermediate buffers for device %s",
comp_dev->qat_dev->name);
return NULL;
}

Expand All @@ -246,17 +246,50 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
", size required %d, size created %zu",
inter_buff_mz_name, mz_start, mz_start_phys,
full_size, memzone->len);
size_of_ptr_array, memzone->len);

array_of_pointers = (struct array_of_ptrs *)mz_start;
for (i = 0; i < num_im_sgls; i++) {
uint32_t curr_sgl_offset =
offset_of_sgls + i * sizeof(struct qat_inter_sgl);
struct qat_inter_sgl *sgl =
(struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
const struct rte_memzone *mz;
struct qat_inter_sgl *sgl;
int lb;
array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;

snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
"%s_inter_buff_%d", comp_dev->qat_dev->name, i);
mz = rte_memzone_lookup(inter_buff_mz_name);
if (mz == NULL) {
mz = rte_memzone_reserve_aligned(inter_buff_mz_name,
full_size,
comp_dev->compressdev->data->socket_id,
RTE_MEMZONE_IOVA_CONTIG,
QAT_64_BYTE_ALIGN);
if (mz == NULL) {
QAT_LOG(ERR,
"Can't allocate intermediate buffers for device %s",
comp_dev->qat_dev->name);
while (--i >= 0) {
snprintf(inter_buff_mz_name,
RTE_MEMZONE_NAMESIZE,
"%s_inter_buff_%d",
comp_dev->qat_dev->name,
i);
rte_memzone_free(
rte_memzone_lookup(
inter_buff_mz_name));
}
rte_memzone_free(memzone);
return NULL;
}
}

QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
", size required %d, size created %zu",
inter_buff_mz_name, mz->addr, mz->iova,
full_size, mz->len);

array_of_pointers->pointer[i] = mz->iova;

sgl = (struct qat_inter_sgl *) mz->addr;
sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
sgl->num_mapped_bufs = 0;
sgl->resrvd = 0;
Expand All @@ -268,8 +301,8 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
#endif
for (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) {
sgl->buffers[lb].addr =
mz_start_phys + offset_of_flat_buffs +
(((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size);
mz->iova + offset_of_flat_buffs +
lb * buff_size;
sgl->buffers[lb].len = buff_size;
sgl->buffers[lb].resrvd = 0;
#if QAT_IM_BUFFER_DEBUG
Expand All @@ -281,7 +314,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
}
#if QAT_IM_BUFFER_DEBUG
QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:",
mz_start, offset_of_flat_buffs + 32);
memzone->addr, size_of_ptr_array);
#endif
return memzone;
}
Expand Down Expand Up @@ -444,6 +477,16 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
/* Free intermediate buffers */
if (comp_dev->interm_buff_mz) {
char mz_name[RTE_MEMZONE_NAMESIZE];
int i = qat_gen_config[
comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;

while (--i >= 0) {
snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
"%s_inter_buff_%d",
comp_dev->qat_dev->name, i);
rte_memzone_free(rte_memzone_lookup(mz_name));
}
rte_memzone_free(comp_dev->interm_buff_mz);
comp_dev->interm_buff_mz = NULL;
}
Expand Down Expand Up @@ -607,7 +650,8 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,

tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
&compress_qat_dummy_ops;
QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
QAT_LOG(ERR,
"This QAT hardware doesn't support compression operation");

} else {
tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
Expand Down Expand Up @@ -656,11 +700,6 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,
int i = 0;
struct qat_device_info *qat_dev_instance =
&qat_pci_devs[qat_pci_dev->qat_dev_id];
if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
return 0;
}

struct rte_compressdev_pmd_init_params init_params = {
.name = "",
.socket_id = qat_dev_instance->pci_dev->device.numa_node,
Expand Down

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