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soc: arm: xilinx_zynqmp: Refactor for multi-arch support.
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue zephyrproject-rtos#20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io> | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config SOC_XILINX_ZYNQMP | ||
bool |
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# Copyright (c) 2019 Lexmark International, Inc. | ||
# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io> | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config SOC_XILINX_ZYNQMP | ||
bool "Xilinx ZynqMP" | ||
config SOC_XILINX_ZYNQMP_RPU | ||
bool "Xilinx ZynqMP RPU" | ||
select CPU_CORTEX_R5 | ||
select SOC_XILINX_ZYNQMP | ||
select GIC_V1 | ||
select MULTI_LEVEL_INTERRUPTS | ||
select 2ND_LEVEL_INTERRUPTS |
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/* | ||
* Copyright (c) 2019 Lexmark International, Inc. | ||
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io> | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
* | ||
*/ | ||
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#include <autoconf.h> | ||
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#if defined(CONFIG_SOC_XILINX_ZYNQMP_RPU) | ||
#include <arch/arm/aarch32/cortex_r/scripts/linker.ld> | ||
#endif |