Extend qemu_cortex_r5 test coverage #20217

stephanosio · 2019-10-29T12:29:11Z

At the time of writing, the qemu_cortex_r5 board based on xilinx_zynqmp SoC is only able to run very basic non-multitasking samples and tests (e.g. hello_world sample).

In order to improve test coverage on the qemu_cortex_r5 platform and facilitate CI testing of the ARM Cortex-R port, QEMU needs to be patched to provide a better emulation of the RPU of the Xilinx ZynqMP SoC; at the same time, incorrect xilinx_zynqmp SoC implementation on Zephyr needs to be fixed.

QEMU Tasks

~~PATCH: arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters~~
(https://patchwork.kernel.org/patch/10717697)
~~PATCH: xlnx-zynqmp: add the timers~~
(https://patchwork.kernel.org/patch/10048347)
~~PATCH: xlnx-zynqmp: add PL390 GIC for RPU~~
(WIP)

A pull request incorporating the above patches is to be made on zephyr_rtos/qemu. As for the new patch(es), a pull request will be made on Xilinx/qemu and, hopefully, Xilinx will submit an upstream patch.

It seems the hard-coded qemu machine type -machine xlnx-zcu102 (currently being used as the default "run" environment by qemu_cortex_r5 board) is simply obsolete. Both RPU GIC and TTCs are properly mapped when emulating with -machine arm-generic-fdt using the latest zcu102-arm.dts from Xilinx/qemu-devicetrees.

Add Xilinx QEMU (qemu-system-xilinx-aarch64) sdk-ng#138 Add arm-generic-fdt machine type support to Zephyr SDK qemu (this machine type is currently only available in Xilinx/qemu)

Zephyr Tasks

Add sdk 0.11.0-alpha-5 ci-dockerfiles#55 Add Zephyr SDK 0.11.0-alpha-5 to the CI docker image
boards: arm: qemu_cortex_r5: Use arm-generic-fdt machine type. #20298 Modify qemu_cortex_r5 board qemu emulation to use arm-generic-fdt machine type
Refactor and fix xilinx_zynqmp SoC definition #20267 Fix incorrect xilinx_zynqmp dts (the current dts used by RPU is really that of APU, especially the GIC-400 mapping that only applies to APU)
interrupt_controller: gic: Support multiple GIC versions #21508 Implement PL390 GICv1 support
~~Implement tickless capability for xlnx_psttc_timer #19869 Implement tickless API for Cadence TTC system timer driver~~ (withdrawn)

Note

Since the current Zephyr architecture cannot support AMP of Zynq APUs and RPUs in one project, we should consider the APU and RPU to be different hardware platforms (i.e. consider renaming xilinx_zynqmp to xilinx_zynqmp_rpu; when Cortex-A support is added in the future, add xilinx_zynqmp_apu; qemu_cortex_a53 should then utilise xilinx_zynqmp_apu). -> This has been addressed in the PR Refactor and fix xilinx_zynqmp SoC definition #20267.
Implement tickless capability for xlnx_psttc_timer #19869 was withdrawn from this issue due to the severe timing instability in the Xilinx QEMU that makes it impossible to emulate tickless mode operation.

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stephanosio · 2019-10-29T12:35:05Z

cc @bbolen @wjliang @carlocaione @ioannisg

stephanosio · 2019-10-29T14:57:18Z

Sample qemu RPU boot command line using the latest dts:
qemu-system-aarch64 -machine arm-generic-fdt -nographic -dtb ~/Dev/xilinx-qemu-devicetrees/build/zcu102-arm.dtb -serial mon:stdio -device loader,file=/home/stephanos/Dev/zephyr-public/zephyr/tests/kernel/timer/timer_monotonic/build_cr5/zephyr/zephyr.elf,cpu-num=4 -device loader,addr=0xff5e023c,data=0x80008fde,data-len=4 -device loader,addr=0xff9a0000,data=0x80000218,data-len=4

andrewboie · 2019-12-19T08:14:19Z

What debugger is that?

stephanosio · 2019-12-19T08:18:41Z

What debugger is that?

@andrewboie It is gdb with the gdb-dashboard.

https://github.com/cyrus-and/gdb-dashboard

ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue zephyrproject-rtos#20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue zephyrproject-rtos#20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue zephyrproject-rtos#20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

This commit removes the ignore tags for the tests that work after the changes in the PR zephyrproject-rtos#20267. In the future, this ignored testing tag list will be further reduced as critical bugs for the qemu_cortex_r5 platform are addressed (see zephyrproject-rtos#20217). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

This commit removes the ignore tags for the tests that work after the changes in the PR #20267. In the future, this ignored testing tag list will be further reduced as critical bugs for the qemu_cortex_r5 platform are addressed (see #20217). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

stephanosio · 2020-01-07T18:47:30Z

All PRs merged.

wentongwu · 2020-02-25T08:09:26Z

@stephanosio not familiar with this platform, but what's the CPU clock frequency for this QEMU, thanks

stephanosio · 2020-02-25T09:00:37Z

@stephanosio not familiar with this platform, but what's the CPU clock frequency for this QEMU, thanks

@wentongwu In terms of QEMU, it is meaningless to talk about the CPU clock frequency for obvious reasons.

When running on real hardware (ZCU102), the clock frequency would depend on various configurations (e.g. on-board oscillator frequency, PLL configuration, ... handled by the PMU).

wentongwu · 2020-02-25T12:03:35Z

@stephanosio yes, for normal mode we don't need that, but I'm trying to enable QEMU icount mode for qemu_cortex_r5, and it need CPU clock frequency to do some math, if any interest, please take a look #22904 and #14173 . Thanks

stephanosio added Enhancement Changes/Updates/Additions to existing features area: Drivers area: ARM ARM (32-bit) Architecture area: Testing platform: Xilinx Xilinx labels Oct 29, 2019

stephanosio self-assigned this Oct 29, 2019

stephanosio mentioned this issue Oct 30, 2019

Add arm-generic-fdt machine support in qemu-system-aarch64 zephyrproject-rtos/sdk-ng#132

Closed

stephanosio mentioned this issue Oct 31, 2019

Add Xilinx QEMU (qemu-system-xilinx-aarch64) zephyrproject-rtos/sdk-ng#138

Merged

This was referenced Oct 31, 2019

Refactor and fix xilinx_zynqmp SoC definition #20267

Merged

boards: arm: qemu_cortex_r5: Use arm-generic-fdt machine type. #20298

Merged

stephanosio mentioned this issue Nov 5, 2019

Cortex-R Port Improvement for 2.2 #19698

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This was referenced Nov 7, 2019

cmake: Add initial support for Zephyr SDK 0.11 #20408

Closed

arch: arm: Add Cortex-R floating point configuration support. #20469

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stephanosio mentioned this issue Nov 12, 2019

Cortex-R Improvement #20594

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stephanosio closed this as completed Jan 7, 2020

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Extend qemu_cortex_r5 test coverage #20217

Extend qemu_cortex_r5 test coverage #20217

stephanosio commented Oct 29, 2019 •

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Extend qemu_cortex_r5 test coverage #20217

Extend qemu_cortex_r5 test coverage #20217

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