This tool is a Verilog IEEE 1364-2005 parser library written in
Nim. The output is an abstract syntax tree (AST)
intended to be used by other tools to process source files written in Verilog.
For example, vls is a language server
implementation that relies on this library to analyze the source code.
It's also possible to extract the tokenized source code directly from the lexer or from the preprocessor.
Coming soon.
Releases follow semantic versioning to determine how the version number is incremented. If the specification is ever broken by a release, this will be documented in the changelog.
If you discover a bug or what you believe is unintended behavior, please submit an issue on the issue board. A minimal working example and a short description of the context is appreciated and goes a long way towards being able to fix the problem quickly.
This tool is free software released under the MIT license.
vparse is maintained by Marcus Eriksson.