Error in reading bit file in qpsk overlay

[HeshamMohammedHussien]

Hi All;
I try to reimplement the design through generating the file from system generator, then exporting the bit file from Vivado 2020.1. I've generated the bit file successfully and include it within the same path included in pynq image. However when I try to read it from the QPSK overlay this error appear . If I use the original file it works. Do I missed any permission request during bit file generation?

[dnorthcote]

Hi Hesham,

Looks like the bitstream didn't upload correctly. Could you reupload, and maybe wait a minute before doing anything.

Let me know if this works,

Thanks,
David.

[HeshamMohammedHussien]

Hi David,
Thanks for you reply. I've tried to reupload the bit file but the same error appeared.
Let me describe the procedure that I've followed to generate the bit file:

• I've downloaded the Simulink model that is shared for QPSK transmitter.
• I've add a constant to one of the constellation points. (just a small modification).
• I use the system generator tool to generate the Vivado project( Vivado 2020.1).
• I've written the constrain file to enable bit generation.
• The synthesis, implementation and bit generation process are done successfully.
• I've drag and drop the bit file and hwdef files to jupyter lab.
• I've copied the two file in bitstream location.
• I've modified the qpsk_overlay.py code to read the imported bit file.
• Finally, I run pynq_data converter.py code.

Notice: I've flash the bit file from Vivado to the board as a check if the generated bit file to check if it is compatible to the board or not.
Based on the above steps, Could you help me where the error might be? Is there a permission to generate or import the bit file?
Thanks in advance.

[dnorthcote]

Hello,

Are you able to tell me the size of the bitstream after its loaded into Jupyter?

Can you also confirm the address location where you are saving the bitstream file?

By your account, everything should work, but looks like something still isn't right,

Thanks,
David.

[HeshamMohammedHussien]

Hi David,
Thanks for your quick response.
I've attached a snap shot includes the old bit files and my generated bit files where there are located in the same path.
Do you think something wrong in the importing process?
Best,
Hesham

[jogomojo]

Hi @HeshamMohammedHussien. What path are you getting your .hwh file from? Can you also confirm you are building the bitstream in Vivado for the ZCU111 board (or at least the XCZU28DR-2FFVG1517E chip). It would be helpful if you uploaded your hwh file as well for us to look at.

[dnorthcote]

Hi @HeshamMohammedHussien,

If you have resolved your issue, please let me know so I can close this issue,

Kind regards,
David.

[HeshamMohammedHussien]

Hi David,
I try to go through the steps one more time, but I did not know what is build stands for. Is there an extra step for obtaining the bit file because I did not face any build instruction in the process?
Also, Could you share the constraint file to compare mine?
Best,

[dnorthcote]

Hi @HeshamMohammedHussien

After bitstream generation using Vivado, you should be able to locate the hwh and bitstream files from the following locations:

hwh — ./rfsoc_qpsk/rfsoc_qpsk.srcs/sources_1/bd/block_design/hw_handoff/block_design.hwh
bitstream — ./rfsoc_qpsk/rfsoc_qpsk.runs/impl_1/block_design_wrapper.bit

These files should be loaded into the following address on the board:
usr/local/lib/python3.6/dist-packages/rfsoc_qpsk/bitstream

They should both be named rfsoc_qpsk.hwh and rfsoc_qpsk.bit,

Kind regards,
David.

Also, Could you share the constraint file to compare mine?

All constraints we use are in this repository.

[HeshamMohammedHussien]

Hi David,
Sorry for bothering you, but I am a bit new with the RFSOC board.
I am attached a snap shot for the path of the bit file but it is called .bin, Are the the same?
Also I attach the hwh and .Bin as requested before.
Appreciated your effort.

Bit files.zip

[dnorthcote]

Hi @HeshamMohammedHussien,

I think you may need more support with understanding core concepts about Xilinx design tools. I'm going to point you to a few resources that I think may be useful for you. I will then close this issue, as the main problem isn't about this repository.

FPGA Developer have a nice video on how to develop a PYNQ system from scratch:

• Video Link — https://www.fpgadeveloper.com/2018/03/create-a-custom-pynq-overlay-for-pynq-z1.html/

Cathal's DMA tutorial is available once you have a hang of the Vivado workflow:

• Part 1 — https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133
• Part 2 — https://discuss.pynq.io/t/tutorial-pynq-dma-part-2-using-the-dma-from-pynq/3134

Although old, the Zynq book tutorials outline a general Vivado workflow.

• Tutorial Download — http://www.zynqbook.com/php/getDownload.php?req=1

Hope everything works out okay. If there is a bug in the repository, please report it here. However, if you need support using PYNQ, then please use the resources I've indicated above or ask in the forums https://discuss.pynq.io/c/support/

Kind regards,
David.