RISC-Processor-32-bit-Verilog

32 bit RISC Processor
RISC Processor

Reference

[1]Basic Idea:https://www.eg.bucknell.edu/~csci320/2014-fall/#!single.md

Future Plans

In my next project I am going to implement the concept of Single Cycle Processor with better design idea. Please give me suggestions how I can improve this project and if you are a student like me, we can have a discussion and you are always welcome to discuss and contact me.

Name		Name	Last commit message	Last commit date
Latest commit History 52 Commits
README.md		README.md
alu.v		alu.v
control.v		control.v
execute.v		execute.v
factorial.asm		factorial.asm
input_memory		input_memory
instruction_fetch.v		instruction_fetch.v
memory.v		memory.v
memory_access.v		memory_access.v
operand_fetch.v		operand_fetch.v
program.asm		program.asm
register_file.v		register_file.v
risc.jpg		risc.jpg
risc.v		risc.v
risc_tb.v		risc_tb.v
write_back.v		write_back.v

sudhamshu091/RISC-Processor-32-bit-Verilog

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RISC-Processor-32-bit-Verilog

Reference

[1]Basic Idea:https://www.eg.bucknell.edu/~csci320/2014-fall/#!single.md

Future Plans

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