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This is a hardware implementation of the DCPU-16 cpu designed by @notch for his new game 0x10c.
It is entirely written in RTL level Verilog and is synthesisable. While functional, there is still plenty of room for improvements, optimisations etc.
The DCPU16 is designed with a single-issue 8-stage integer pipeline with a maximum speed of 1-clock cycle per stage. It takes at least 8-clock cycles to complete a single instruction and this is split into two stages of 4-clock cycles each.
As a result, the maximum effective instruction rate is 4-clock cycles per instruction.
- Fetch (FE) - fetches the instruction.
- Decode (DE) - decodes the instruction.
- Address A (EA) - calculates the effective address for operand A.
- Address B (EB) - calculates the effective address for operand B.
- Load A (LA) - loads the operand A.
- Load B (LB) - loads the operand B.
- Execute (EX) - executes the operation.
- Save A (SA) - saves the result back to A.
Caveat Emptor!
It's only been tested with the sample programme provided by @notch. It works. There are still likely to be bugs in the code. If you spot any, feel free to fix it and send me a pull request.
You can simulate the files using Icarus Verilog. You should also install gtkwave as a waveform viewer, unless you already have something else to use.
If you do not have any of it installed, you will need to do that first. To do this in Ubuntu, simply issue:
$ sudo apt-get -y install iverilog gtkwave
To simulate the DCPU16 RTL code, do the following from within the project directory.
$ cd sim/
$ ./iversim verilog/dcpu16_sim.v
This will dump out a LXT file that you can view with gtkwave:
$ gtkwave dump.lxt
That's it!
Have fun hacking!