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Pipelined DCPU-16 Verilog Implementation
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doc Removed documentation file. May 30, 2012

DCPU-16 Microprocessor

Copyright (C) 2012 Shawn Tan All Rights Reserved.

Released under LGPL3.


This project is a hardware implementation of the DCPU-16 microprocessor designed by Marcus Persson (@notch) for his new game 0x10c.

The core is written entirely in synthesisable Verilog RTL.


It has an 8-stage integer pipeline, split into two parts, each with 4-stages. Each stage can run within a single clock cycle. Therefore, the maximum effective rate for executing an instruction is 4-clock cycles.

  • Fetch (FE) - fetches instructions from memory.
  • Decode (DE) - decodes the instruction.
  • Calc A (EA) - calculates the effective address for A.
  • Calc B (EB) - calculates it for B.
  • Load A (LA) - loads operand A.
  • Load B (LB) - loads operand B.
  • Execute (EX) - executes the instruction.
  • Store A (SA) - stores operand A.


Currently synthesises on a Spartan 6 to about:

  • 500 Slices @ 149 MHz


It is not FPGA proven, yet.

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