VHDL Programming Training for FPGA

by Tertiary Infotech Pte. Ltd

These are the exercise files used for VHDL Programming Training for FPGA course.

The course outline can be found in

https://www.tertiarycourses.com.sg/vhdl-programming-fpga-training.html

https://www.tertiarycourses.com.my/vhdl-programming-fpga-training.html

Day 1

FPGA Design FLOW
Motivation

Module 1 : Introduction to VHDL

• Library & Packages
• Entity/Modes
• Architecture

Module 2: VHDL Data Types

• Language Elements
• Identifiers
• Literals
• Types
• Conversion (Advance)
• Object Types
• TEXTIO

Module 3: Operators

• Logical Operator
• Relational Operators
• Arithmetic Operator
• Resize function
• Shift Operators
• Multiplying Operators
• Miscellaneous Operators

Module 4: Concurrent Statements

• Aggregates
• Drivers
• Concurrent Statement 
• Component Instantiation
• Block Statement
• Generate Statement

Module 5: Sequential Statements

• Process statement / Sensitivity List
• Wait statement
• IF statement
• Case statement
• Loop
• Define Range
• Variables
• Variables Vs Signals

Module 6: Configuration

• Generic
• Operator Overloading
• Attributes

Module 7: Lab Exercise

• Combinational Logic

Day 2

Module 8: State Machine

1. Mealy 
2. Moore

Module 9: Simulation

• Steps of simulation / Simulation Deltas
• Inertia Delay / Transport delay
• Test bench

Module 10: Lab Activities

• Design Entry
• Writing VHDL code 
• Test bench 
• Simulating VHDL code with Vivado (Xilinx)
• Synthesize the code