MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64 #4480
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Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 tianocore@d9f1cac tianocore@e83d841 and below the commit for ARM and AArch64 implementation tianocore@c0959b4 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw
Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual
This API is first introduced in the below commits for IA32 and x64 d9f1cac e83d841 and below the commit for ARM and AArch64 implementation c0959b4
This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe
Cc: Andrei Warkentin andrei.warkentin@intel.com
Cc: Evan Chai evan.chai@intel.com
Cc: Sunil V L sunilvl@ventanamicro.com
Cc: Tuan Phan tphan@ventanamicro.com
Signed-off-by: Yong Li yong.li@intel.com
Reviewed-by: Sunil V L sunilvl@ventanamicro.com