Add release notes for 12.4.0 release

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

- boots from eNVM
- uses lim memory for RAM
- has console on uart 0
- has procfs enabled
- has most of nsh commands enabled

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps
- Remove most of the the build steps, leave just arm-12 and riscv;
	arm-12 has a build for stm32f7, and riscv for mpfs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…ptimized version in tiiuae repo

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…iver to re-initialize on rx timeout

If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the
already implemented mpfs_txtimeout_expiry.

This is a temporary workaround for a bug where IF might be UP and working but packets can only
be transmitted. Receive side just doesn't work at all.

The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while
the IF is up.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card
into high-speed mode, but currently NuttX doesn't support this.

With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with
25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with
50MHz interface clock.

This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…ootloader

This removes the need to have all the DDR/clock configuration related
"LIBERODEFS" flags defined, when not building a standalone/coldboot
configuration

All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

This is not the correct way to do this, but it gives a nice perf. boost

Disable macOS builds for now.

All other commands are disabled in send_recv().

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>

…ef and forward declare devif_loopback

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

… that takes care of the need for loopback

Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board.
Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.

Fix build warning when CONFIG_STM32F7_AUTONEG is not set

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…ved IO area in protected build

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Just a temporary patch, need to implement some kind of scalable solution
for this. It might be a good idea to map something else for the user
to avoid using ecall to enter the kernel for simple reads ?

Also, increase the L3 table size

There is no make step executed for this directory before the Kconfigure,
so all Kconfig's just need to be in-tree

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

sendfifo() function need enable BWR_IE before checking if BWE is enabled
to avoid BWE to be activated between the BWE check and BWR interrupt
enabling, which causes the interrupt to be missed and Data Timeout error.

The user i/o area goes over 4MB, so need more page tables

Add FPGA serial support, including console capabilities.
FPGA has UARTs from 0-7, so all UARTs starting from 5
depend on FPGA.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

These are always the same as FPGA peripheral clock, so use that directly

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Don't turn off FIC3 clk which would terminate all other
peripherals depending on it.

Also add a few missing undefs.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

…mage

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…river change

Revert:
commit 1975878
Author: Huang Qi <huangqi3@xiaomi.com>
Date:   Mon Apr 11 18:42:24 2022 +0800

    arch/risc-v: Apply common mtime driver to mtime based chps

    Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

As this breaks the systick

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…tloader

This is actually the same table as entrypoints, so just use the same data, which
can be set before booting any of the harts

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…d by NuttX vs. opensbi

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

This loads the OpenSBI from eNVM into the zerodevice.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Use a configuration register to set the upper address lines [37:32] for USB DMA engine.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>

Don't allow unaligned access with the DMA requests.
Return -EFAULT in case the provided address is unaligned.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

The TLS alignment requires more room in the stack, which means more
_initial_ heap is required to accomodate the stack.

Why 2x TLS_MAXSTACK ? No idea. This is a temporary fix, like the +1 page
extra above.

After read training, check also that the eye is centered properly. Sometimes
after the training the width is long enough, but it is not centered.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Just verify that the delay for the selected clock != 0

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Corrections to CA training verify step. The original copied from HSS didn't
make sense in all aspects:
- The check is not per lane, so it should be out of the "for (lane_sel" loop.
- The check wasn't proper. The expected outcome is just a vector of increasing numbers
  separated enough

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

If the remote end just closes an endpoint and no longer handles it,
the system is prone to intensive cpu polling via mpfs_write_tx_fifo()
especially if the device side doesn't know a thing about what the
remote did.

Fix this by marking the EP as dead, which will skip all writes causing
unnecessary polling. The EP is back in business if the remote end
sends some data (rx) or the connection is re-established.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Currently the irq handler checks many reserved bits, which is
a waste of resources:

1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
   defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
   rest are reserved

Fix this by checking only the relevant bits.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Provide support for NET_RPMSG_TRANSFER only:

"It is recommended to drop all messages with commands other than
NET_RPMSG_TRANSFER in function net_rpmsg_drv_ept_cb() of the
flight controller."

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Set HPWORK as default workqueue for eth ISR work

Previously, address 0x03b70000u was written with shift bits
that only changed the bit width, not the mode. HS mode is
changed via 0x03B90100, which is required, according to Jedec
specs, for DDR mode. HS mode was not applied before. Enforce
DDR mode (50 MHz) for now.

The real boost, however, comes from removing the DMA limitation
at 0x08xxxxxx address space, which now seems unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Set the LOCKED bit when the final ddr segmentatition is
in place. Otherwise the system is prone to potential
security issues if the config is altered later. Once the
LOCKED bit is set, the register may no longer be changed.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Remove unnecessary junk, just build icicle (we don't care about the rest)

Don't use the upstream build targets

This is the only way to get the external module "uavcanlib" to work
inside the px4 kernel.

If an alternate solution, e.g. moving uavcanlib to user space is implemented
this hack should be removed.

Now all registers are defined

This adds support for detecting various tamper events.
The interrupt handler makes noise at every detection.

Perhaps easiest test is to attach JTAG debugger.

TAMPER_TESTS -define has some nonexisting (not in repos)
calls, perhaps could remove it alltogether.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

…ization to _calc_imm

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

MPUCFG registers are used to enforce memory protection for DMA master
devices.

This is not the right place to modify DMA memory protection values.

Why not? These are designed to protect other AMP mode instances. Opening
the entire SoC's memory for the USB DMA kind of defeats this purpose.

Also, the driver cannot know how to configure these registers correctly,
only opening up the whole SoC "works".

After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.

This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
  DEBUGASSERT(nwords > 0);

…nsole off

By setting "isconsole" to false, mpfs_serial stops outputting to console.

This can be used to disable output to debug console in low level.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.

Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

…g/deinitializing bus

Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Add more error status codes to help debugging in the future.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block
- Use the i2c mutex to protect the reset; in case there are several devices
  on the same bus, and one of them resets the bus, reset must not occur in
  the middle of another device's transfer.
- Move irq attach to the i2c_init as the irq detach is in i2c_deinit

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Add sanity checks for debugging possible errors in the driver.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…s in warm boot

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

It is possible that a PLIC IRQ is claimed but not completed at warm
reset. This occurs at least if there is a fault in the middle of irq
handler execution.

To recover from such situation, we can complete all IRQ:s in PLIC;
this completes any already claimed IRQ, but has no effect on IRQs
which are not claimed or not enabled.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

Add method to lock an MPUCFG entry. Locking means the value of the register
cannot be changed until the SoC is reset.

The macro was wrong

Set i_size for shmfs objects

up_addrenv_page_wipe can be used to wipe a single page of memory.

When shmfs_truncate is called, it uses shmfs_alloc_object to create the
physical backing for the shm file. However, the allocated physical
memory returned by mm_pgalloc is not cleared when CONFIG_BUILD_KERNEL is
set, which is a clear POSIX violation:

https://pubs.opengroup.org/onlinepubs/9699919799/functions/truncate.html

"If the file was previously shorter than length, its size is increased,
and the extended area appears as if it were zero-filled."

For FLAT and PROTECTED modes zalloc is used, so the violation affects
KERNEL mode only.

… warnings

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

   Support runtime phy selection based on a list
   supplied by board.h
   For Example:

   #define BOARD_ETH0_PHY_LIST                   \
	{                                        \
		"LAN8742A",                      \
		MII_PHYID1_LAN8742A,             \
		MII_PHYID2_LAN8742A,             \
		MII_LAN8740_SCSR,                \
		0,                               \
		0xffff,                          \
		MII_LAN8720_SPSCR_10MBPS,        \
		MII_LAN8720_SPSCR_100MBPS,       \
		MII_LAN8720_SPSCR_DUPLEX,        \
		22                               \
	},                                       \
	{                                        \
		"TJA1103",                       \
		MII_PHYID1_TJA1103,              \
		MII_PHYID2_TJA1103,              \
		0xffff,                          \
		18,                              \
		0xffff,                          \
		0                       ,        \
		MII_LAN8720_SPSCR_100MBPS,       \
		MII_LAN8720_SPSCR_DUPLEX,        \
		45,                              \
	},                                       \

  Allow a board to specify a list of PHYs.
  Then use this list, at run-time, to select and use the
  PHY populated on the board.

…onfigs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

This reverts commit c87ad9f.

This reverts commit 1870a5c.

…x/size optimized version in tiiuae repo"

This reverts commit cd75eb6.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

…make sure we use MSP as the stack pointer

When entering the function from an external bootloader, the CPU could be using PSP. But the following
code expects MSP to be in use.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>