Merge pull request #453 from mithro/or1k-rom-size-fix

targets: Working on ROM size fixes.
timvideos · Sep 1, 2018 · 2b3ff04 · 2b3ff04
2 parents 2939f93 + 754f0a3
commit 2b3ff04
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Showing 21 changed files with 177 additions and 87 deletions.
diff --git a/.travis.yml b/.travis.yml
@@ -130,6 +130,15 @@ jobs:
   - stage: Targets
     env: C=or1k.linux F=linux P=arty        T="net"
 
+  - stage: Targets
+    env: C=or1k.linux F=linux P=atlys       T="net"
+
+  - stage: Targets
+    env: C=or1k.linux F=linux P=opsis       T="net"
+
+  - stage: Targets
+    env: C=or1k.linux F=linux P=nexys_video T="net"
+
   #--------------------------------------------
   # Video Targets
   #--------------------------------------------

diff --git a/targets/arty/base.py b/targets/arty/base.py
@@ -118,11 +118,13 @@ class BaseSoC(SoCSDRAM):
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/arty/net.py b/targets/arty/net.py
@@ -26,6 +26,10 @@ class NetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
+        if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') == 'or1k':
+            kwargs['integrated_rom_size'] = 0x10000
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(

diff --git a/targets/atlys/base.py b/targets/atlys/base.py
@@ -186,17 +186,19 @@ class BaseSoC(SoCSDRAM):
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
     mem_map = {
-        "spiflash":     0x20000000,  # (default shadow @0xa0000000)
+        "spiflash": 0x20000000,  # (default shadow @0xa0000000)
     }
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = 75*1000000
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x4000,
-            with_uart=True,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 

diff --git a/targets/atlys/net.py b/targets/atlys/net.py
@@ -25,6 +25,10 @@ class NetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
+        if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') == 'or1k':
+            kwargs['integrated_rom_size'] = 0x10000
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(

diff --git a/targets/basys3/base.py b/targets/basys3/base.py
@@ -62,11 +62,13 @@ class BaseSoC(SoCCore):
     mem_map.update(SoCCore.mem_map)
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCCore.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCCore.__init__(self, platform, clk_freq, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/cmod_a7/base.py b/targets/cmod_a7/base.py
@@ -37,11 +37,13 @@ class BaseSoC(SoCCore):
     mem_map.update(SoCCore.mem_map)
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCCore.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCCore.__init__(self, platform, clk_freq, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/galatea/base.py b/targets/galatea/base.py
@@ -11,6 +11,8 @@
 from litedram.phy import s6ddrphy
 from litedram.core import ControllerSettings
 
+from gateware import info
+
 from targets.utils import csr_map_update
 
 
@@ -173,26 +175,38 @@ class BaseSoC(SoCSDRAM):
     csr_peripherals = (
         "spiflash",
         "ddrphy",
+        "info",
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
+    # FIXME: Add spiflash
+    #mem_map = {
+    #    "spiflash": 0x20000000,  # (default shadow @0xa0000000)
+    #}
+    #mem_map.update(SoCSDRAM.mem_map)
+
     def __init__(self, platform, **kwargs):
-        clk_freq = 50*1000000
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
 
         if 'expansion' in kwargs:
             tofe_board_name = kwargs.get('expansion')
             del kwargs['expansion']
         else:
             tofe_board_name = None
 
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x4000,
-            with_uart=True,
-            **kwargs)
+
+        clk_freq = 50*1000000
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 
+        # Basic peripherals
+        self.submodules.info = info.Info(platform, self.__class__.__name__)
+
         # sdram
         sdram_module = MT41J128M16(self.clk_freq, "1:4")
         self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(

diff --git a/targets/mimasv2/base.py b/targets/mimasv2/base.py
@@ -189,17 +189,20 @@ class BaseSoC(SoCSDRAM):
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=None
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
 
-        cpu_reset_address = self.mem_map["spiflash"]+platform.gateware_size
+        kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
+        if os.environ.get('JIMMO', '0') == '0':
+            kwargs['uart_baudrate']=19200
+        else:
+            kwargs['uart_baudrate']=115200
 
         clk_freq = (83 + Fraction(1, 3))*1000*1000
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            #integrated_rom_size=0x8000,
-            integrated_rom_size=None,
-            integrated_sram_size=0x4000,
-            uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))],
-            cpu_reset_address=cpu_reset_address,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 
@@ -219,7 +222,7 @@ def __init__(self, platform, **kwargs):
 
         bios_size = 0x8000
         self.add_constant("ROM_DISABLE", 1)
-        self.add_memory_region("rom", cpu_reset_address, bios_size)
+        self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
         self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
 
         # sdram

diff --git a/targets/minispartan6/base.py b/targets/minispartan6/base.py
@@ -79,22 +79,27 @@ class BaseSoC(SoCSDRAM):
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
     mem_map = {
-        "spiflash":     0x20000000,  # (default shadow @0xa0000000)
+        "spiflash": 0x20000000,  # (default shadow @0xa0000000)
     }
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
+
         clk_freq = 80*1000000
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 
-        self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
+        # Basic peripherals
+
 
         self.submodules.info = info.Info(platform, self.__class__.__name__)
+        self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
 
 
         self.submodules.spiflash = spi_flash.SpiFlash(

diff --git a/targets/neso/base.py b/targets/neso/base.py
@@ -97,11 +97,13 @@ class BaseSoC(SoCSDRAM):
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/netv2/base.py b/targets/netv2/base.py
@@ -90,11 +90,13 @@ class BaseSoC(SoCSDRAM):
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/nexys_video/base.py b/targets/nexys_video/base.py
@@ -101,12 +101,13 @@ class BaseSoC(SoCSDRAM):
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x8000
+
         clk_freq = int(100e6)
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x8000,
-            with_uart=False,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
 
         self.submodules.crg = _CRG(platform)
         self.crg.cd_sys.clk.attr.add("keep")

diff --git a/targets/nexys_video/net.py b/targets/nexys_video/net.py
@@ -26,6 +26,10 @@ class NetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
+        if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') == 'or1k':
+            kwargs['integrated_rom_size'] = 0x10000
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(

diff --git a/targets/opsis/base.py b/targets/opsis/base.py
@@ -234,6 +234,11 @@ class BaseSoC(SoCSDRAM):
     mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
+
         clk_freq = 50*1000000
 
         if 'expansion' in kwargs:
@@ -242,11 +247,8 @@ def __init__(self, platform, **kwargs):
         else:
             tofe_board_name = None
 
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x4000,
-            with_uart=False,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 

diff --git a/targets/opsis/net.py b/targets/opsis/net.py
@@ -27,6 +27,10 @@ class NetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
+        if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') == 'or1k':
+            kwargs['integrated_rom_size'] = 0x10000
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(

diff --git a/targets/pipistrello/base.py b/targets/pipistrello/base.py
@@ -188,11 +188,15 @@ class BaseSoC(SoCSDRAM):
 
 
     def __init__(self, platform, **kwargs):
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
+
         clk_freq = (83 + Fraction(1, 3))*1000*1000
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size=0x8000,
-            integrated_sram_size=0x4000,
-            **kwargs)
+
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
+
         self.submodules.crg = _CRG(platform, clk_freq)
         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
 

diff --git a/targets/saturn/base.py b/targets/saturn/base.py
@@ -182,14 +182,23 @@ class BaseSoC(SoCSDRAM):
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
+    # FIXME: Add spiflash
+    #mem_map = {
+    #    "spiflash": 0x20000000,  # (default shadow @0xa0000000)
+    #}
+    #mem_map.update(SoCSDRAM.mem_map)
+
     def __init__(self, platform, **kwargs):
-        clk_freq=(31 + Fraction(1, 4))*1000*1000
+        if 'integrated_rom_size' not in kwargs:
+            kwargs['integrated_rom_size']=0x8000
+        if 'integrated_sram_size' not in kwargs:
+            kwargs['integrated_sram_size']=0x4000
+
+
+        clk_freq = (31 + Fraction(1, 4))*1000*1000
+
+        SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
 
-        SoCSDRAM.__init__(self, platform, clk_freq,
-            integrated_rom_size  = 0x8000,
-            integrated_sram_size = 0x4000,
-            **kwargs
-        )
         self.submodules.crg = _CRG(platform, clk_freq)
 
         # sdram