arty/base: Account for CPU endianness, platform clock divider in SPI …

…flash controller.
timvideos · Nov 20, 2018 · bfd548e · bfd548e
1 parent 0baa62d
commit bfd548e
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/platforms/arty.py b/platforms/arty.py
@@ -115,7 +115,7 @@ class Platform(XilinxPlatform):
     # module objects.
     spiflash_model = "n25q128a13"
     spiflash_read_dummy_bits = 10
-    spiflash_clock_div = 4
+    spiflash_clock_div = 2
     spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
     spiflash_page_size = 256
     spiflash_sector_size = 0x10000

diff --git a/targets/arty/base.py b/targets/arty/base.py
@@ -149,7 +149,8 @@ def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
         self.submodules.spiflash = spi_flash.SpiFlash(
                 spiflash_pads,
                 dummy=spiflash_dummy[spiflash],
-                div=2)
+                div=platform.spiflash_clock_div,
+                endianness=self.cpu.endianness)
         self.add_constant("SPIFLASH_PAGE_SIZE", 256)
         self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
         self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)