This project was intended to demonstrate some of my understanding and usage of the Verilog language.
I have implemented a Single-Cycle MIPS processor with forwarding enabled. I used Verilog for implementation and tested my implementation using a Verilog Test Bench. This implemenation includes an ALU, PC, Registers, and Memory.
It supports several commands:
- add, addu, addi
- sub, subi
- slt
- nor, or
- and
- lw, sw
- beq