chips/earlgrey/chip_config: increase CW310 FPGA clock frequencies #3639
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This is in accordance with an upstream change [1]. While the register set and other chip attributes are frozen for EarlGrey, the clock frequencies are not. This change will also be backported to the lowRISC/opentitan `earlgrey_es` branch [2]. [1]: lowRISC/opentitan#19368 [2]: lowRISC/opentitan#19479
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Ping @cfrantz |
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How does this relate to |
Yeah ... good point. We'll want to put this PR on hold until we have a new stable bitstream to increment to. My bad. |
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LGTM after lowRISC/opentitan#19479 gets submitted on the earlgrey_es branch.
We'll need to update the OpenTitan SHA afterwards.
Note that the changes to clock frequencies don't change any of the Earlgrey hardware implementation - they only change the base clocks for the FPGA synthesis.
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@cfrantz Is there an updated bitstream? |
I've tested this change with opentitan/master@HEAD and with opentitan/earlgrey_es@7df72d61f536e9babb343219232783e5e49f7ceb. Both worked. The earlgrey_es bitstream is available from the opentitan-bitstreams GCP bucket here: https://storage.googleapis.com/opentitan-bitstreams/earlgrey_es/bitstream-7df72d61f536e9babb343219232783e5e49f7ceb.tar.gz I think this can go in as long as we update the |
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Awesome! |
bradjc
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…requencies. I failed to test this myself (I was unable to find the rsa.tbf that board/opentitan/README.md thought would exist) so I used the already-tested commit here: tock#3639 (comment)
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Replaced by #3703 |
Pull Request Overview
This is in accordance with an upstream change 1. While the register set and other chip attributes are frozen for EarlGrey, the clock frequencies are not. This change will also be backported to the lowRISC/opentitan
earlgrey_esbranch 2.Testing Strategy
This pull request was tested by running Tock on latest OpenTitan master on a CW310 FPGA.
TODO or Help Wanted
N/A
Documentation Updated
Updated the relevant files inor no updates are required./docs,Formatting
make prepush.