[fpga] Increase CW310 base clock frequency to 24 MHz #19368
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Since we are entering a phase where there might be longer-running tests for silicon validation, I figured I'd take up some of the slack on the FPGA build. The increase in frequencies does not materially affect build times, so CI should not be impacted. It also doesn't materially decrease test times in CI, since most of the delays there are in software build, bitstream programming, and UART output, haha. |
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This core file was moved over to the top_englishbreakfast folder. It is not used for Earl Grey, which includes the related RTL files directly in the FPGA chip-level cores.
Put entropy_src into auto mode so the test doesn't run out. Signed-off-by: Alexander Williams <awill@opentitan.org>
Set clock frequencies for CW310 to the following clk_main: 24 MHz clk_io_div4: 6 MHz Also improve the SPI_HOST timing constraints to have the correct max frequency, in addition to multicycle paths reflecting the correct capture edges. Signed-off-by: Alexander Williams <awill@opentitan.org>
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What I had forgotten is that this will also impact SCA measurements. So for SCA measurements we should generate a custom bitstream with a 10 MHz main clock again in the future. But since we were anyway creating custom bitstreams for KMAC already (to switch the masking on), I think this is not a big issue. @wettermo , @vrozic , @bilgiday , @johannheyszl |
This is in accordance with an upstream change [1]. While the register set and other chip attributes are frozen for EarlGrey, the clock frequencies are not. This change will also be backported to the lowRISC/opentitan `earlgrey_es` branch [2]. [1]: lowRISC/opentitan#19368 [2]: lowRISC/opentitan#19479
Set clock frequencies for CW310 to the following
This should enable performing fast I2C mode at closer to 400 kHz, possibly enabling faster than 400 kHz I2C (fast-plus mode).