The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.
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Updated
Jun 23, 2023 - C
The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.
Implementation and evaluation of Pentium_m, GShare, One_bit, Bimode & Perceptron branch predictors within the Xeon X5550 Gainestown Nehalem microarchitecture
This repository contains code for various branch predictors. These were written as part of a classroom exercise for the CS810: Advanced Computer Architecture course at IIT Dharwad.
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