RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
-
Updated
Mar 19, 2018 - SystemVerilog
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
Network on Chip Implementation written in SytemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Senior Project for [ECE5545]: AXI NOC with Embedded ECC and HARQ
Add a description, image, and links to the noc topic page so that developers can more easily learn about it.
To associate your repository with the noc topic, visit your repo's landing page and select "manage topics."