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Thanks always for whole lot of fantastic work. I am currently interested in testing AMD CPUs to see if it also allocates L1 MSHRs for all kinds of prefetch instructions similarly as you reported the below thread with SKX.
I wonder this uarch-bench would work well for AMD CPUs or it needs some modifications. It seems it should work as it is but it would be great if you can confirm.
Thanks,
The text was updated successfully, but these errors were encountered:
Hi Travis,
Thanks always for whole lot of fantastic work. I am currently interested in testing AMD CPUs to see if it also allocates L1 MSHRs for all kinds of prefetch instructions similarly as you reported the below thread with SKX.
https://stackoverflow.com/questions/19472036/does-software-prefetching-allocate-a-line-fill-buffer-lfb/47959139#47959139
I wonder this uarch-bench would work well for AMD CPUs or it needs some modifications. It seems it should work as it is but it would be great if you can confirm.
Thanks,
The text was updated successfully, but these errors were encountered: