SDIO polling reads are timing dependent

[mcudev]

The SDIO RX FIFO is only 128 bytes large. The read block size is 512 bytes. Delays encountered while performing polling reads with HAL_SD_ReadBlocks are susceptible to FIFO overruns and other abnormal results (like timeouts where only a portion of the data is returned before the peripheral gets into a weird state).

This is most easily reproduced by stepping through with the debugger.

INSTRUCTION_CACHE_ENABLE being 1 in stm32f4xx_hal_conf.h is one thing hiding the issue and saving us usually at full speed. But, other delays can still cause the problem to manifest itself.

In fact, INSTRUCTION_CACHE_ENABLE == 0 and disabling the SDIO_BUS_WIDE_4B (that is, just using a 1-bit bus) works just as well. But, with that config, introducing delay with the debugger still causes RX FIFO overrun.

I was mainly researching this area to see what was possible without PREFETCH_ENABLE and INSTRUCTION_CACHE_ENABLE because PREFETCH_ENABLE can't be used at some voltage levels.

Perhaps SDIO reads should be interrupt driven, or DMA? Maybe the read block size can be lowered? I tried lowering it to 128 bytes, but was getting CRC errors, so either that's not a great approach or I missed changing something else.

[mcudev]

closing as informational