fix top level clock for atlys board

initialize boot and jump ROMs from file instead of using the IP CORE generator

memory_controller.v

@@ -40,24 +40,30 @@ module memory_controller(
 );
 
   // internal data out pins
-  wire [7:0] Do_boot_rom;
   wire [7:0] Do_high_ram;
-  wire [7:0] Do_int_table;
 
   // internal r/w enables
-  wire cs_boot_rom;
-  wire cs_high_ram;
-  wire cs_int_table;
+  wire cs_boot_rom;
+  wire cs_jump_rom;
+  wire cs_high_ram;
 
-  // remapped addresses
-  wire [6:0] A_high_ram;
-  wire [6:0] A_int_table;
+  // remapped addresses
+  wire [6:0] A_jump_rom;
+  wire [6:0] A_high_ram;
 
   // when 8'h01 gets written into $FF50 the ROM is disabled
-  reg rom_enable;
+  reg rom_enable;
+
+  // ROMs
+  reg [7:0] boot_rom [0:255];
+  reg [7:0] jump_rom [0:9];
 
-  boot_rom br(A, Do_boot_rom);
-  interrupt_table it(A_int_table, Do_int_table);
+  initial begin
+    $readmemh("data/boot.rom", boot_rom, 0, 255);
+    $readmemh("data/jump.rom", jump_rom, 0, 126);
+  end
+
+  // TODO: replace with async ram
   high_ram hr(A_high_ram, Di_cpu, clock, cs_high_ram && !wr_n, Do_high_ram);
 
   always @ (posedge clock)
@@ -73,7 +79,7 @@ module memory_controller(
         case(A)
           16'hFF46:
           begin
-            // DMA
+            // TODO: DMA
           end
           16'hFF50: if (Di == 8'h01) rom_enable <= 1'b0;
         endcase
@@ -89,18 +95,18 @@ module memory_controller(
     (A >= 16'hFE00 && A < 16'hFEA0) || // oam
     (A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46); // registers (except for DMA)
 
-  assign cs_boot_rom = rom_enable && A < 16'h0100;
+  assign cs_boot_rom = rom_enable && A < 16'h0100;
+  assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
   assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
-  assign cs_int_table = A >= 16'hFEA0 && A < 16'hFF00;
 
   assign cs_interrupt = A == 16'hFF0F || A == 16'hFFFF;
   assign cs_sound = A >= 16'hFF10 && A <= 16'hFF3F; // there are some gaps here
   assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
   assign cs_joypad = A == 16'hFF00;
 
-  // remap addresses
+  // remap addresses
+  assign A_jump_rom = A - 16'hFEA0;
   assign A_high_ram = A - 16'hFF80;
-  assign A_int_table = A - 16'hFEA0;
 
   // Main RAM + Cartridge
   assign A = A_cpu;
@@ -115,9 +121,9 @@ module memory_controller(
   assign rd_video_n = rd_cpu_n;
 
   assign Do_cpu =
-    (cs_boot_rom) ? Do_boot_rom :
+    (cs_boot_rom) ? boot_rom[A_cpu] :
     (cs_high_ram) ? Do_high_ram :
-    (cs_int_table) ? Do_int_table :
+    (cs_jump_rom) ? jump_rom[A_jump_rom] :
     (cs_interrupt) ? Do_interrupt :
     (cs_timer) ? Do_timer :
     (cs_sound) ? Do_sound :

s6atlys.v

@@ -45,28 +45,40 @@ module s6atlys(
 
   //
   // Clocks (GameBoy clock runs at ~4.194304 MHz)
+  // 
+  // FPGABoy runs at 33.5 MHz, mostly to simplify the video controller.
+  //  Certain cycle sensitive modules, such as the CPU and Timer are
+  //  internally clocked down to the GameBoy's normal speed.
   //
 
-  // Core Clock: 33.5 MHz (33.3333 MHz)
-  wire coreclk, core_clock;
-  DCM_SP core_clock_dcm (.CLKIN(CLK_50M), .CLKFX(coreclk), .RST(1'b0));
-  defparam core_clock_dcm.CLKFX_DIVIDE = 3;
-  defparam core_clock_dcm.CLKFX_MULTIPLY = 1;
-  defparam core_clock_dcm.CLK_FEEDBACK = "NONE";
+  // Core Clock: 33.5 MHz (33.3333 MHz)
+  wire coreclk, core_clock;
+  DCM_SP core_clock_dcm (.CLKIN(CLK_100M), .CLKFX(coreclk), .RST(1'b0));
+  defparam core_clock_dcm.CLKFX_DIVIDE = 6;
+  defparam core_clock_dcm.CLKFX_MULTIPLY = 2;
+  defparam core_clock_dcm.CLK_FEEDBACK = "NONE";
   BUFG core_clock_buf (.I(coreclk), .O(core_clock));
 
+  // TODO: HDMI Clocks
+  //  No idea what these look like yet.
+
+  // TODO: Debug Clock 
+  //  The clock should mux between the core clock and a switch based 
+  //  debug clock to allow a simple method of stepping through instructions.
+
+  // Game Clock
+  wire clock;
+  assign clock = core_clock;
+
   // Initial Reset
   wire reset_init, reset;
-  SRL16 reset_sr(.D(1'b0), .CLK(CLK_50M), .Q(reset_init),
+  SRL16 reset_sr(.D(1'b0), .CLK(CLK_100M), .Q(reset_init),
                  .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
   defparam reset_sr.INIT = 16'hFFFF;
 
-  // TODO debug clock
-  wire clock;
-  assign clock = core_clock;
-
-  // TODO reset switch
-  wire reset_sync = 0;
+  // Power Button
+  wire reset_sync;
+  debounce debounce_reset_sync(reset_init, core_clock, !SW[7], reset_sync);
   assign reset = (reset_init || reset_sync);
 
   //
@@ -139,7 +151,7 @@ endmodule
 ////////////////////////////////////////////////////////////////////////////////
 
 module debounce (reset, clock, noisy, clean);
-  parameter DELAY = 500000;   // .01 sec with a 50Mhz clock
+  parameter DELAY = 1000000;   // .01 sec with a 100Mhz clock
   input reset, clock, noisy;
   output clean;