remove () from asUInt() (#72)

ucb-bar · Apr 26, 2023 · 9deaf1d · 9deaf1d
1 parent bf09515
commit 9deaf1d
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/main/scala/MulAddRecFN.scala b/src/main/scala/MulAddRecFN.scala
@@ -236,7 +236,7 @@ class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
     val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
     val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
     val notCDom_nearNormDist = notCDom_normDistReduced2<<1
-    val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt().zext
+    val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
     val notCDom_mainSig =
         (notCDom_absSigSum<<notCDom_nearNormDist)(
             sigWidth * 2 + 3, sigWidth - 1)

diff --git a/src/main/scala/RoundAnyRawFNToRecFN.scala b/src/main/scala/RoundAnyRawFNToRecFN.scala
@@ -181,7 +181,7 @@ class
             )
 //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
 //***  M.S. BIT OF SUBNORMAL SIG?
-        val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt().zext
+        val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
 
         common_expOut := sRoundedExp(outExpWidth, 0)
         common_fractOut :=