Merge pull request #1860 from ucb-bar/remove_generatemodelstagemain

Remove tapeout.GenerateModelStageMain

.github/scripts/remote-do-rtl-build.sh

@@ -53,5 +53,5 @@ do
     export COURSIER_CACHE=$REMOTE_COURSIER_CACHE
     export JVM_MEMORY=10G
     export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR
-    make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info ${mapping[$key]}
+    make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR ${mapping[$key]}
 done

common.mk

@@ -192,19 +192,8 @@ else
 	echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@
 endif
 
-$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
+$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
 	rm -rf $(GEN_COLLATERAL_DIR)
-	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\
-		--no-dedup \
-		--output-file $(SFC_FIRRTL_BASENAME) \
-		--output-annotation-file $(SFC_ANNO_FILE) \
-		--target-dir $(GEN_COLLATERAL_DIR) \
-		--input-file $(FIRRTL_FILE) \
-		--annotation-file $(FINAL_ANNO_FILE) \
-		--log-level $(FIRRTL_LOGLEVEL) \
-		-X none \
-		--allow-unrecognized-annotations)
-	-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE)
 	firtool \
 		--format=fir \
 		--export-module-hierarchy \
@@ -216,10 +205,10 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
 		--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
 		--repl-seq-mem \
 		--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
-		--annotation-file=$(SFC_ANNO_FILE) \
+		--annotation-file=$(FINAL_ANNO_FILE) \
 		--split-verilog \
 		-o $(GEN_COLLATERAL_DIR) \
-		$(SFC_FIRRTL_FILE)
+		$(FIRRTL_FILE)
 	$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
 	touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
 # DOC include end: FirrtlCompiler

docs/Customization/index.rst

@@ -29,8 +29,6 @@ We also provide information on:
 
 - The boot process for Chipyard SoCs
 
-- Examples of FIRRTL transforms used in Chipyard, and where they are specified
-
 We recommend reading all these pages in order. Hit next to get started!
 
 .. toctree::
@@ -50,5 +48,4 @@ We recommend reading all these pages in order. Hit next to get started!
    Incorporating-Verilog-Blocks
    Memory-Hierarchy
    Boot-Process
-   Firrtl-Transforms
    IOBinders

docs/Tools/FIRRTL.rst

@@ -7,6 +7,4 @@ Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which
 An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
 Once the transformations are done, a Verilog file is emitted and the build process is done.
 
-To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
-
 For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.