Fix post-syn/par sim

[harrisonliew]

In #1324 I consolidated the input files for simulation, but broke post-syn/par simulation as a result.
This PR makes sure that no TOP Verilog files make it to post-syn/par sims.
Being tested by @bdngo
@moresa75

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[bdngo]

I am currently testing this with ChipTop post-synthesis flows, currently depending on a RocketTile and a backing scratchpad.