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PLL integration example + FlatChipTop/TestHarness #1427

Merged
merged 9 commits into from
Apr 9, 2023
Merged

PLL integration example + FlatChipTop/TestHarness #1427

merged 9 commits into from
Apr 9, 2023

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jerryz123
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@jerryz123 jerryz123 commented Apr 6, 2023

  • Provides a new WithPLLSelectorDividerClockGenerator to replace the default WithDividerOnlyClockGenerator. WithPLLSelectorDividerClockGenerator adds regmapped clock-mux, clock-divider, and a fake PLL with regmapped control. The intention is for future chips to create custom clock binders following this pattern
  • Adds a ChipConfigs file with ChipLikeRocketConfig, that sets up crossings, clock gen, I/O more realistically.
  • Adds FlatChipTop and FlatTestHarness, to demonstrate how to use a custom TestHarness+ChipTop with Chipyard, bypassing the IOBinders/HarnessBinders if necessary (this should only be done as a last resort).
make CONFIG=ChipLikeRocketConfig run-binary BINARY=../../tests/hello.riscv

For custom ChipTop/TestHarness... do

make CONFIG=ChipLikeRocketConfig MODEL_PACKAGE=chipyard.example MODEL=FlatTestHarness run-binary BINARY=../../tests/hello.riscv

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

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@harrisonliew harrisonliew left a comment

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Looks good for the most part without testing.

@jerryz123 jerryz123 merged commit 1097073 into main Apr 9, 2023
@noahgaertner
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Does this require/assume the PLL is actually a PLL (because internal clock/external clock edges need to be synchronous or something), or could some other clock multiplier be inserted instead?

@jerryz123
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The FakePLL in WithPLLSelectorDividerClockGenerator can be replaced with any block that emits clocks.

@jerryz123 jerryz123 deleted the pll branch April 18, 2023 01:48
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3 participants