(VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus

[DecodeTheEncoded]

When evaluating a RV32 design(just add WithRV32 in the RocketVCU118Config) on vcu118. The beatBytes is 4, and therefore dataBits of the MemoryBus will be 32. However the AXI that goes to MIG core is predefined as 64bits wide. Therefore, there is a data field width mismatch here, causing the RV32 design can not access DDR4 of VCU118 successfully. See WithDDRMem HarnessBinder for vcu118 below:

class WithDDRMem extends OverrideHarnessBinder({
  (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
    th match { case vcu118th: VCU118FPGATestHarnessImp => {
      require(ports.size == 1)
      println(s"the ddr port ${ports}")
      val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1)
      println(s"the val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1) from mig island is ${bundles.head.params.dataBits}")
      println(s"the val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1) from tllink island is ${ports.head.head.params.dataBits}")
      val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
      bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
      ddrClientBundle <> ports.head
    } }
  }
})

It turns out that this harness binder implementation breaks the diplomatic negotiation. It just conducts a chisel connection between two chisel bundles(ddrClientBundle <> ports.head) instead of diplomatic connection. Even though the width of the data field is normally determined by downward TLManager according to TLImp. But this harness binder impl breaks that parameter propagation process from manager to client(there are two negotiation ends: memTLNode in CanHaveMasterTLMemPort and val ddrClient = TLClientNode(Seq(inParams.master)) in VCU118FPGATestHarness), therefore the data field width mismatch occurs.
This PR adds a TLWidthWidget to hide the width difference, I changed ddrNode := ddrClient to the following loc:
ddrNode := TLWidthWidget(dp(XLen) / 8) := ddrClient
And the WithRV32 configuration runs successfully on vcu118
Related PRs / Issues:
#1481

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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[DecodeTheEncoded]

@jerryz123 Hi Jerry, I filed this PR, do you mind taking a look? Thanks.